Error while installing spike simulator

[raiyyanfaisal09]

I am trying to run the verification for the core. I have installed the toolchain as instructed. However, while trying to install and build spike simulator. I am seeing these issues. I have gone through the same steps that have been mentioned on the README for https://github.com/lowRISC/riscv-isa-sim

the command I used to configure the tool was

../configure --enable-commitlog --enable-misaligned --prefix=/home/rmasumda/projects/spike_cosim

and then I ran make and that is when I encountered that error.

My Environment

I am using 15fbd5680e44da699f828c67db15345822a47ef6 version of the IBEX. I am using 2017.12-1 version of Synopsys VCS, 3.900 version of Verilator, 7.2.0 version of GCC and 3.7.3 version of python

The Linux is CentOS, version 7.

Can you please tell me what the problem is and how can it be fixed?

[rswarbrick]

Hi there,

I'm sorry, but I can't actually find that SHA in either Ibex or our spike clone (riscv-isa-sim). Please could you reply with a description of what exactly you were building?

Thanks!

[raiyyanfaisal09]

Hi @rswarbrick,

I have been able to build it.

However, I have used the following commands to configure the spike.

../configure --prefix=/home/rmasumda/projects/spike_cosim --enable-commitlog --enable-misaligned --without-boost --without-boost-asio --without-boost-regex

One of my colleague was recommended to use this command instead of the one mentioned in the README. After using this command to build the spike simulator and carrying out the next steps, which I was successful at. I am seeing some other problems while running the DV sims.

These are the errors I am seeing while running the following command to run the DV sim.

make --keep-going IBEX_CONFIG=opentitan SIMULATOR=vcs ISS=spike ITERATIONS=1 SEED=1 TEST=riscv_rand_jump_test WAVES=0 COV=1

And the error that I am seeing is :

Generating core configuration file Building randomized test generator make[1]: [out/metadata/instr.gen.build.stamp] Error 1 make[1]: Target `all' not remade because of errors. make: [run] Error 2

I cannot see tb.compile.stamp being generated and also instr.gen.build.stamp.

& when I go on to take a look at the instr_gen compile.log, I am seeing :

Error-[SV-EEM-SRE] Scope resolution error /home/rmasumda/projects/ibex_riscv/dv/uvm/core_ibex/riscv_dv_extension/ibex_debug_triggers_overrides.sv, 13 riscv_instr_pkg, "ibex_hardware_triggers_debug_rom_gen::type_id::create" Target for scope resolution operator does not exist. Token 'ibex_hardware_triggers_debug_rom_gen' is not a class/package. Originating module 'riscv_instr_pkg'. Check that class or package exists with referred token as the name.

& this is what I am seeing in tb/compile_tb.log

Error-[UM] Undefined macro /home/rmasumda/projects/ibex_riscv/dv/uvm/core_ibex/env/core_ibex_dut_probe_if.sv, 92 Undefined macro exists as: 'DV_CREATE_SIGNAL_PROBE_FUNCTION'
"/home/rmasumda/projects/ibex_riscv/dv/uvm/core_ibex/env/core_ibex_dut_probe_if.sv", 92: token is 'DV_CREATE_SIGNAL_PROBE_FUNCTION' DV_CREATE_SIGNAL_PROBE_FUNCTION(signal_probe_rf_ren_a, rf_ren_a)

What have I done wrong here?

[rswarbrick]

Hmm, this is odd. It might be that the problem is only shown by VCS (we mostly use Xcelium for our testing). This is a bit silly, but could you try hacking the ibex_debug_triggers_overrides.sv file to swap the order of the classes? Maybe SystemVerilog doesn't technically allow a namespace to be used earlier in the file than it's definition? (On the plus side, this would be a super easy fix!)

[raiyyanfaisal09]

@rswarbrick, that did work! thanks! However, I could still see the other error I mentioned above. There are some `defines used and I cannot see them being defined anywhere. Is there a file missing ?

Error-[UM] Undefined macro /home/rmasumda/projects/ibex_riscv/dv/uvm/core_ibex/env/core_ibex_dut_probe_if.sv, 92 Undefined macro exists as: 'DV_CREATE_SIGNAL_PROBE_FUNCTION'
"/home/rmasumda/projects/ibex_riscv/dv/uvm/core_ibex/env/core_ibex_dut_probe_if.sv", 92: token is 'DV_CREATE_SIGNAL_PROBE_FUNCTION' DV_CREATE_SIGNAL_PROBE_FUNCTION(signal_probe_rf_ren_a, rf_ren_a)

[raiyyanfaisal09]

I also tried to run the sims with Xcelium and its complaining about a totally different file.

make[1]: [out/metadata/tb.compile.stamp] Error 1 Generating core configuration file Building randomized test generator Running randomized test generator to create assembly file /home/rmasumda/projects/ibex_riscv/dv/uvm/core_ibex/out/run/tests/riscv_arithmetic_basic_test.1/test.S Compiling riscvdv test assembly to create binary at /home/rmasumda/projects/ibex_riscv/dv/uvm/core_ibex/out/run/tests/riscv_arithmetic_basic_test.1/test.bin make[1]: Target `all' not remade because of errors. make: [run] Error 2

& the following is the error from compile_tb.log

if (!m_mem.addr_exists(addr)) begin
                     |

xmvlog: *E,NOTCLM (/home/rmasumda/projects/ibex_riscv/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv,180	25): addr_exists is not a class item. if (!m_mem.addr_exists(addr)) begin
xmvlog: *E,NOTFXX (/home/rmasumda/projects/ibex_riscv/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv,180	25): Expecting a function name [10.3.3(IEEE)]

These are the first 2 error messages followed by

DV_CREATE_SIGNAL_PROBE_FUNCTION(signal_probe_rf_ren_a, rf_ren_a) | xmvlog: *E,NOTDIR (/home/rmasumda/projects/ibex_riscv/dv/uvm/core_ibex/env/core_ibex_dut_probe_if.sv,92|33):DV_CREATE_SIGNAL_PROBE_FUNCTION: not a recognized directive or macro [2.7.3][16.3.1][16(IEEE)].

[rswarbrick]

Ah, well the missing macro is also caused by an ordering problem. I think VCS is internally concatenating files in a different order from what Xcelium happens to choose. That this causes a problem is a bug in our code! :-D Fortunately, the fix is easy. If you look at e.g. clk_rst_if.sv, you'll see it include the definition we need. I think you can just copy/paste some of that code and add something like this to core_ibex_dut_probe_if.sv:

`ifndef VERILATOR
  `include "dv_macros.svh"
`endif

If that fixes things, we should take both changes that we've found so far!

For the other error, I'm a bit confused. The message looks like it's saying that it doesn't know that addr_exists makes sense here. But I think that m_mem is of type mem_model and it looks like mem_model.svh defines that function (on line 96). The message about DV_CREATE_SIGNAL_PROBE_FUNCTION is also rather confusing. The macro is defined in dv_macros.svh. Maybe something had already gone awry before the error message came out?

So I'm sorry that I haven't properly fixed things for you with Xcelium. If you're still finding issues there, is there any chance you could give a step-by-step sequence for us to reproduce the error? Thanks!

[raiyyanfaisal09]

Hi @rswarbrick, Thanks for the response. That definitely helped me get over the first issue I was seeing. However, I wasn't able to solve the issue with mem_model call. I also forgot to mention, I was seeing an error related to the DPI calls in ibex_if_stage.sv file (that I suspect is a DPI call related to icache?) before I saw this error I mentioned above & since we are not using icache at this moment I thought of commenting it out. Thats when I saw the issue I mentioned above related to m_mem_model.

So that brings me to my question - what could possibly be causing an issue there ?

Also, I pulled the latest yesterday and I don't remember the commit number in which I was seeing those errors. Hence, I am seeing totally new set of errors now.

This is what I am currently seeing with VCS as the simulator: ( @GregAC )

Error-[FCIWCS] Invalid 'with' clause specification /home/rmasumda/projects/ibex_riscv/dv/uvm/core_ibex/fcov/core_ibex_fcov_if.sv, 646 core_ibex_fcov_if, "priv_mode_irq_cross" The 'with' clause specified on the cross bin does not have any impact and is invalid; it should contain at least one occurence of the constituent coverpoint names. Please remove or correct the clause and compile

Syntactically it looks fine, however I don't see definition of some of the enum data type variables. I am not sure if that is really the issue, I am only suspecting here. The reason being, greping the variable 'PRIV_LVL_M' in 'dv' only shows me the instances where it is used and not the actual definition (if at all the error is actually related to this variable and not something else).

Would really appreciate if you can give me some insight into how to solve this issue.

I have also been wondering, if I am supposed to be pulling a certain commit that is clean and tested and not do so randomly. If you do recommend to take in the new updates that is clean and tested then is there a way to know what and when to pull in those updates?

Thanks!

[rswarbrick]

Hi there! It turns out that I also spent some time last week getting stuff working with VCS. I think that PR #2037 should get everything working for you again. It'll probably be merged soonish, but it's not quite in yet.

Note that the VCS error that you've pasted above actually seems to be VCS getting confused! My "fix" in that PR is basically rewriting things in an equivalent way that VCS happens to understand. Sigh...

Would you mind trying again with the version at the tip of that PR? I'm sorry for the slow reply.

[raiyyanfaisal09]

Hi @rswarbrick, Sorry for the delay on this issue. I have been busy with some other engagements. Thank you for your response and fixing errors seen with VCS. Those errors are gone. However, I have been seeing some new errors now.

First of all, I saw errors related to spike simulator. It was complaining about line 79 of compile_tb.py script, that it isn't able to find riscv-riscv and riscv-fdt in the pkgconfig directory in lib of my spike installation directory. I therefore removed those two and added riscv-fesvr (since riscv-fesvr and riscv-disasm were the only two files I was able to see there).

After making changes there, that error then changed to this :

In file included from /home/rmasumda/projects/IBEX_DV/riscv_ibex_dv/dv/uvm/core_ibex/common/ibex_cosim_agent/spike_cosim_dpi.cc:10:0: \

/home/rmasumda/projects/IBEX_DV/riscv_ibex_dv/dv/cosim/spike_cosim.h:16:10: fatal \ error: riscv/devices.h: No such file or directory

include "riscv/devices.h"

      ^~~~~~~~~~~~~~~~~

compilation terminated. make[3]: *** [spike_cosim_dpi.d] Error 1 cc1plus: warning: command line option '-std=c99' is valid for C/ObjC but not for \ C++ g++ -w -pipe -DVCSMX -DUVM_DPI_DO_TYPE_CHECK -fPIC --std=c99 -fno-extended-identifiers \ -I/home/rmasumda/projects/IBEX_DV/spike_cosim//home/rmasumda/projects/IBEX_DV/spike_cosim/include \ -I/home/rmasumda/projects/IBEX_DV/riscv_ibex_dv/dv/cosim -O -I/cad/adi/apps/synopsys/vcs/2022.06/include \ -c /home/rmasumda/projects/IBEX_DV/riscv_ibex_dv/dv/cosim/cosim_dpi.cc cc1plus: warning: command line option '-std=c99' is valid for C/ObjC but not for \ C++ In file included from /home/rmasumda/projects/IBEX_DV/riscv_ibex_dv/dv/cosim/spike_cosim.cc:5:0: \

/home/rmasumda/projects/IBEX_DV/riscv_ibex_dv/dv/cosim/spike_cosim.h:16:10: fatal \ error: riscv/devices.h: No such file or directory

include "riscv/devices.h"

      ^~~~~~~~~~~~~~~~~

compilation terminated. make[3]: [spike_cosim.d] Error 1 make[3]: Target `product_order' not remade because of errors. make[2]: [product_clean_order] Error 2 make[2]: Target product' not remade because of errors. make[2]: Leaving directory/home/rmasumda/projects/IBEX_DV/riscv_ibex_dv/dv/uvm/core_ibex/out/build/tb/vcs_simv.csrc' \

Would really appreciate you helping me fix those issues. Does it have to do with spike simulators installation or what am I missing here.

I have been using the following command to run the simulation.

make --keep-going IBEX_CONFIG=opentitan SIMULATOR=vcs ISS=spike ITERATIONS=1 SEED=1 TEST=riscv_arithmetic_basic_test WAVES=0 COV=0 COSIM=1

I pulled in master since I figured this (https://github.com/lowRISC/ibex/pull/2037 ) commit must have been merged and must have become stable by now.

Looking forward to learning soon from you.

Thanks, Raiyyan

[rswarbrick]

Hi there! It sounds like things aren't properly installed. In particular, riscv/devices.h should appear in the include directory of a Spike installation. I'd suggest looking through your installation and working out where that file is. (I took the stupid option here of find /opt/spike -name devices.h, but obviously you'll need a different root path)