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lowRISC / ibex

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
https://www.lowrisc.org
Apache License 2.0
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Spike not generating csrrw and compressed instructions #2168

Open yuhbj opened 4 months ago

yuhbj commented 4 months ago

image Running RTL simulation at out/seed-6496/rtl_sim/riscv_illegal_instr_test.6496/sim.log Comparing traces for out/seed-6496/rtl_sim/riscv_illegal_instr_test.6496 Collecting up results (report at out/seed-6496/regr.log) 0.00% PASS 0 PASSED, 1 FAILED ################################################################################

Details of failing tests

################################################################################ riscv_illegal_instr_test.6496

Test binary: out/seed-6496/instr_gen/asm_test/riscv_illegal_instr_test_0.o UVM log: out/seed-6496/rtl_sim/riscv_illegal_instr_test.6496/sim.log RTL trace: out/seed-6496/rtl_sim/riscv_illegal_instr_test.6496/trace_core_00000000.log

** Note: (vsim-12126) Error and warning message counts have been restored: Errors=0, Warnings=43.

[FAILED]: sim error seen

0.00% PASS 0 PASSED, 1 FAILED