[dv] Implement fault injection test for hardening in register file

[GregAC]

This commit: https://github.com/lowRISC/ibex/commit/35bbdb7b introduces various new hardening mechanisms to the register file. Write a test to inject various faults in these mechanisms. Proposed test should:

• Run a random program using the same RISC-DV test and config as riscv_rand_instr_test
• After a random interval choose a random signal amongst those listed to inject a fault
  • we_a_dec
  • raddr_onehot_a
  • raddr_onehot_b
  • Check an alert has occurred within a bounded number of cycles (bound TBD)

[GregAC]

PR here to implement test: https://github.com/lowRISC/ibex/pull/2182