[tracking] Use Verible's verilog_format for code formatting

[imphil]

Verible's verilog_format is a automatic code formatter. We want to be able to run it on our code base, ultimately in "enforcing" mode, requiring all submissions to be formatted with this tool. This is the same approach we take with clang-format and C/C++ files. This issue is to track the progress towards that.

Ibex TODO:

• [x] Add Verible format support to edalize: https://github.com/olofk/edalize/pull/120
• [x] Add a fusesoc target to our core files: #686
• [x] Add Verible format in non-enforcing mode to CI: #686
• [ ] Document how to use it
• [ ] Clean up existing code once the auto-formatted style matches our expectations.
• [ ] Switch to enforcing mode.

Bugs crashing the formatter:

• [ ] "Some token partitions failed to complete within the search limit" https://github.com/google/verible/issues/346
• [ ] "Formatted output is lexically different from the input" (Mismatched token enums.): https://github.com/google/verible/issues/347

Wrong style produced by the formatter according to the lowRISC style guide:

• [ ] Use two space indents for port and parameter lists: https://github.com/google/verible/issues/40
• [ ] Indentation of initializer lists: https://github.com/google/verible/issues/352
• [ ] Comment in assign statement breaks indentation: https://github.com/google/verible/issues/353

Verible formatter style/readability issues and optional issues:

• [ ] https://github.com/google/verible/issues/228. Workaround for one specific case proposed in https://github.com/lowRISC/ibex/pull/693 to remove the blocking status of this, given that a full solution on the Verible side will take longer.
• [ ] Continue comments in port lists: https://github.com/google/verible/issues/349
• [ ] Line up comments in port lists: https://github.com/google/verible/issues/350
• [ ] Closing parenthesis on its own line: https://github.com/google/verible/issues/351
• [ ] Align assignment expressions: https://github.com/google/verible/issues/357
• [ ] Align variable declarations: https://github.com/google/verible/issues/358
• [ ] Keep condition and ? together in ternaries: https://github.com/google/verible/issues/359
• [ ] Align nested ternaries: https://github.com/google/verible/issues/360
• [ ] Avoid whitespace in bit-selection: https://github.com/google/verible/issues/361

[imphil]

The first set of code changes to get our code in line with what verible format produces is at https://github.com/lowRISC/ibex/pull/1014. The goal is to have that PR cover all the "easy" cases, getting us step-by-step closer to a full equivalence.

[asb]

Thanks for your work in pursuing this, filing upstream issues, and tracking progress.

IMHO #351 should be higher priority - it seems to be a case of producing incorrectly formatted code, which is a much bigger barrier to enforcing verible formatting use than producing output that doesn't match our personal tastes. But once incorrect formatting bugs are addressed I agree with the thrust of your argument in #1014 - don't sweat the small stuff, and in return formatting becomes a solved problem.

We'll want to consult with downstream consumers (OpenTitan) prior to landing a large cosmetic change like #1014. I don't see why it should be problematic at this stage, but it couldn't hurt to explain the plan.