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How to change the address map of 0x0~0x0FFF)FFFF, for exmaple interrupt controller #112

Open nicolast0604 opened 5 years ago

nicolast0604 commented 5 years ago
  1. For rocket chip default configuration,

Generated Address Map 0 - 1000 ARWX debug-controller@0 3000 - 4000 ARWX error-device@3000 1_0000 - 2_0000 R X rom@10000 200_0000 - 201_0000 ARW clint@2000000 c00_0000 - 1000_0000 ARW interrupt-controller@c000000 6000_0000 - 8000_0000 RWX mmio-port-axi4@60000000 8000_0000 - 9000_0000 RWXC memory@80000000

How to change the address map of 0x0~0x0FFF_FFFF, for example interrupt controller?

  1. How to change memory section address?
  2. How to change mmio section address?
  3. Could we remove rocket-chip internal TLROM?
  4. How to change AXI burst length? for example 16.
jrrk commented 5 years ago

It's not a good idea to change the address of the built-in peripherals, they are on a TileLink

bus and there are many built-in assumptions in software and so on that these addresses will not change.

Obviously they could changed in the Chisel if you want to be incompatible with everybody else, but what is the point?

Likewise the main memory address of 0x80000000, if it was changed the ISA tests would break. Furthermore

the AXI interface assumes that the address mask and the memory size are abutted (i.e. bank selection may be

addressed as 0x8XXXXXXX). For the MMIO address there is more flexibility and for LowRISC we use 0x40000000,

you can see this change in src/main/scala/subsystem/Configs.scala https://github.com/freechipsproject/rocket-chip/commit/0e26c3de032f95de80c714bf69207fe88a5d205f#diff-8fec41419d39b456849cd4200efd90f1 in the class WithDefaultMMIOPort. If you really,

really want to change the memory address it can be done in WithDefaultMemPort in the same file. It would not be a

good idea to remove the internal TLROM, because this is used to record the device tree BLOB, BBL and Linux use this

to find where  memory and initial devices are. I don't know if you can change the AXI burst length, this would be a

function of the cache fill/drain parameters, there is limited flexibility here. However you can change the AXI bus width,

known as the beatBytes.

Overall the message is, some parameters (called knobs) are easy to change, others will have far-reaching effects, and

may well result in an RTL that does not pass the ISA tests.

On 26/04/2019 09:14, nicolast0604 wrote:

  1. For rocket chip default configuration,

Generated Address Map 0 - 1000 ARWX debug-controller@0 3000 - 4000 ARWX error-device@3000 1_0000 - 2_0000 R X rom@10000 200_0000 - 201_0000 ARW clint@2000000 c00_0000 - 1000_0000 ARW interrupt-controller@c000000 6000_0000 - 8000_0000 RWX mmio-port-axi4@60000000 8000_0000 - 9000_0000 RWXC memory@80000000

How to change the address map of 0x0~0x0FFF_FFFF, for example interrupt controller?

  1. How to change memory section address?
  2. How to change mmio section address?
  3. Could we remove rocket-chip internal TLROM?
  4. How to change AXI burst length? for example 16.

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