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lowRISC / lowrisc-chip

The root repo for lowRISC project and FPGA demos.
http://www.lowrisc.org/
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Stability issue when loading elf to memory #14

Closed wallento closed 8 years ago

wallento commented 8 years ago

We observed that the verification of the elf in memory hangs occasionally. The verification is temporarily de-activated. Suspects of this issue are:

The problem seems only half-way undeterministic. Adding debug probes to get more details is probably a good start.

wallento commented 8 years ago

@asb @wsong83

wallento commented 8 years ago

After a first round of debug probes I can see that the low level interface is not hanging: It shows sufficient credit for flow control and all FIFO interfaces are ready. The same applies to the interfaces of the MAM. Next round is MAM state.

wallento commented 8 years ago

It seems to be an issue with the logic. The MAM is in idle state. So probably flaw in handling counters or so. Will try to narrow it down soon.

wallento commented 8 years ago

As everything looks good, I am back to suspecting the UART line. As we are running at only 25 MHz, with 3MBaud we have 4 percent shift. This is exactly the boundary usually allowed, so maybe the clock is not adjusted per symbol in the USB-UART chip and transmitting larger chunks of data then creates loss.

wallento commented 8 years ago

The issue is with the last packet in a read reply, but it is not deterministic which one. The packet leaves the FPGA and enters glip, so that I now focus on the software.

wsong83 commented 8 years ago

I assume this issue is potentially fixed. Close it for now, feel free to reopen it again if stuck again.