search

lowRISC / lowrisc-chip

The root repo for lowRISC project and FPGA demos.
http://www.lowrisc.org/
Other
596 stars 148 forks source link

Tilelink conformance level #194

Closed Marc43 closed 3 years ago

Marc43 commented 3 years ago

Hi, I was trying to tell which conformance level of TileLink do you implement but I was not able.

Can you tell me which one?

Thanks and sorry if it is a stupid question!

jrrk2 commented 3 years ago

LowRISC releases up to v0.4 used TileLink-1, v0.5 onwards used TileLink-2. This protocol is confined to inside the Rocket coreplex, all peripherals use AXI or a simple memory bus.

Marc43 commented 3 years ago

Thanks for answering, but, this is not the same as the conformance level, right?

You can implement TL-UL, TL-UH or TL-C, which one of those is implemented between the L1 and the L2?

jrrk2 commented 3 years ago

As I understand it TileLink-1 never worked properly with an L2 cache, so can’t really be described as conformant to anything. TileLink-2 removed the L2 cache from the open-source Rocket database, so again we do not have it in later releases. Once SiFive started the Rocket database was pretty much orphaned. I do not know if SiFive released an L2 cache and if so, what the license terms are.