add supporting VC707 board

[phthinh]

I have add some files for implementing untethered (v0.2) on VC707 board. These files are in a new directory vc707, like kc705. It has just changed one file (/src/main/verilog/chip_top.sv) in upstream. I think it's useful for who has a VC707 board want to play with untethered lowrisc-chip.

[wsong83]

Hello Thinh,

Thanks for feeding the changes back to us. Have you successfully port the untether-v0.2 to your VC707 board? If yes, would you like to set up a new repo, something like the lowrisc-kc705, then we can link it as a submodule in fpga/board.

For this PR, before I do anything, would you please change the file permissions on your computer. There is no need to add execution permission to all files, especially those non-script files.

[wsong83]

Close due to no further response.

[xubaqian]

@phthinh I want to port lowrisc to my VC707 board, can you give me your files in fpga/board/vc707 ?

[jrrk]

It's not a board that LowRISC CIC support at the moment but being a Xilinx supported board, you should have no difficulty finding information online about pinouts and memory interface generator configuration. I believe other users have attempted the same task in the past, but their efforts have not been upstreamed to us as far as I know.

You will find peripherals are significantly different, the video uses HDMI instead of VGA on the newer boards, Ethernet PHYs use a different variant of MII, and clock generators need to be reprogrammed. Because of these reasons we elected not to support multiple boards in our latest release, but doing the port is a worthwhile exercise for somebody that wants to get very familiar with the Vivado tool. I would allow a month's work if you are an expert, about three months if you are skilled in the art but not familiar with the details, or a year if you are a beginner.

For its own sake it might not be worth investing the time, but the experience gained will be invaluable for your future FPGA experiences.

On 09/03/18 09:05, xubaqian wrote:

@phthinh https://github.com/phthinh I want to port lowrisc to my VC707 board, can you give me your files in fpga/board/vc707 ?

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[phthinh]

@xubaqian I have just ported LowRISC untether-v0.2 to VC707 board. This is an old version of LowRISC. I have not attempted for the newer versions. If you look for running untether-v0.2 to VC707 board, I can help. Jonathan is right. It takes time for porting to another board. Instead, I prefer to use the supported board :)

[xubaqian]

Thanks for jrrk's recommend , but I just have vc707 in the short term and want to verify my design. @phthinh I need your help. Thanks.

[phthinh]

The Porting for VC707 board was done as below:

Copy the directory of KC705 Board and rename to VC707. Then, change the following items:

1) ./constraint/pin_plan.xdc to assign the pins for Vertex 7 instead of Kintex 705.

2) ./script/mig_config.prj to assign the pins, and parametters related to DDR3 for Vertex 7 ./script/make_project.tcl

3) ../../../src/main/verilog/chip_top.sv

Using the same make commands of kc705 to build the Demo

[xubaqian]

@phthinh Well, I changed the items as you said according to vc707 Virtex-7 FPGA User Guide. And in vc707 directory, set some environment variables and make bitstream, then add the files in ./generated-src and ./constraint/pin_plan.xdc to a vivado project. When I run Implementation, I encoutered the following errors:

ImplementationPlace Design[Place 30-415] IO Placement failed due to overutilization. This design contains 823 I/O ports
 while the target  device: 7vx485t package: ffg1761, contains only 700 available user I/O. The target device has 700 usable I/O pins of which 0 are already occupied by user-locked I/Os.
 To rectify this issue:
 1. Ensure you are targeting the correct device and package.  Select a larger device or different package if necessary.
 2. Check the top-level ports of the design to ensure the correct number of ports are specified.
 3. Consider design changes to reduce the number of I/Os necessary.
[Place 30-68] Instance clk_IBUF_BUFG_inst (BUFG) is not placed
[Place 30-99] Placer failed with error: 'IO Clock Placer failed'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
[Common 17-69] Command failed: Placer could not place all instances

Can you show me what changes you have made comparing to original files ? This way maybe I can be aware of my mistake more easily. Thanks.

[jrrk]

You should use the VC707 example MIG project as your basis for .xdc files and mig_config.prj going forward. Bearing in mind that each board has its own flavour of DDR memory, you will not be able to use the toplevel of our chip unmodified. If you make an error, Vivado will automatically select a different (incorrect) toplevel, and this could account for the excessive pin count that you are seeing. With the correct toplevel, we have 117 IO and your changes should vary this number by a few. Unless debugging, you should not manually add new files to the project, this is the function of the make project target. Any changes that you make should go in script/make_project.tcl

If you want to debug, issue make cleanall; make project, and if there are no errors, make vivado

This will launch the GUI and you will be able to see errors in detail.

If you add files manually in the GUI, you should update script/make_project.tcl to make your new flow repeatable by others.

I suggest you follow the instructions for the nexys4ddr in the first instance and then treat this result as a reference for your own changes. Trying to take shortcuts will only waste time. It sounds like you probably selected the toplevel of Rocket as your main circuit and this does not match the peripherals you have on the VC707 board, which do not communicate with AXI bus.

On 12/03/18 02:43, xubaqian wrote:

@phthinh https://github.com/phthinh Well, I changed the items as you said according to vc707 Virtex-7 FPGA User Guide. And in vc707 directory, set some environment variables and |make bitstream|, then add the files in ./generated-src and ./constraint/pin_plan.xdc to a vivado project. When I run Implementation, I encoutered the following errors:

|ImplementationPlace Design[Place 30-415] IO Placement failed due to overutilization. This design contains 823 I/O ports while the target device: 7vx485t package: ffg1761, contains only 700 available user I/O. The target device has 700 usable I/O pins of which 0 are already occupied by user-locked I/Os. To rectify this issue: 1. Ensure you are targeting the correct device and package. Select a larger device or different package if necessary. 2. Check the top-level ports of the design to ensure the correct number of ports are specified. 3. Consider design changes to reduce the number of I/Os necessary. [Place 30-68] Instance clk_IBUF_BUFG_inst (BUFG) is not placed [Place 30-99] Placer failed with error: 'IO Clock Placer failed' Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure. [Common 17-69] Command failed: Placer could not place all instances |

Can you show me what changes you have made comparing to original files ? This way maybe I can be aware of my mistake more easily. Thanks.

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[xubaqian]

Oh, there was a problem in my vivado and I reinstalled it and fixed the problem. vivado version 2016.2. I modified the files as phthinh said, but only change -version 2.4 to 4.0 in memory controller because I don't know what else should I modify and this way make project run successfully.

But when make vivado, click run implementation, an error occurred: [Opt 31-67] Problem: A LUT6 cell in the design is missing a connection on input pin I5, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic. The LUT cell name is: dram_ctl/u_mig_7series_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ref_dll_lock. I need help. Thanks.

[jrrk]

As mentioned in the docs, we only support Vivado 2015.4 with that version of LowRISC. i don't know if this is due to IP version incompatibility or synthesis bugs. You may not be affected for that reason but you should at least get it working with this known good version of Vivado before you try any other version. It looks suspicious that the memory IP version has changed and this is also where your error is. You should discard the notion that the latest version of a CAD tool is necessarily the best quite quickly once you become a cynical seasoned engineer.

On 14/03/18 09:02, xubaqian wrote:

Oh, there was a problem in my vivado and I reinstalled it and fixed the problem. vivado version 2016.2. I modified the files as phthinh said, but only change -version 2.4 to 4.0 in memory controller because I don't know what else should I modify and this way |make project| run successfully.

But when |make vivado|, click |run implementation|, an error occurred: |[Opt 31-67] Problem: A LUT6 cell in the design is missing a connection on input pin I5, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic. The LUT cell name is: dram_ctl/u_mig_7series_0_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ref_dll_lock.| I need help. Thanks.

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[xubaqian]

emmm... I generate bitstream, bbl vmlinux and root.bin successfully.
Run spike +disk=busybox-1.21.1/root.bin bbl linux-3.14.41/vmlinux I can see linux boots. Copy bbl vmlinux and root.bin to SD card and rename bbl as boot. Download the bitstream to VC707 and I seeHello, World !on terminal but without linux boots. What's wrong ?

Another question is when make boot in vc707 directory, it shows /bin/bash: data2mem: not found, but I have already export XILINX_VIVADO variable and add it to path.

[jrrk]

When you install Vivado, you need to select the SDK option otherwise data2mem will not be installed. Once it is installed, you need to source the Xilinx supplied init script and not set the path manually. Depending on OS version you may need to unset LD_LIBRARY_PATH manually. Then you will be able to substitute the compiled boot.c for hello.c and hopefully all will be well. If you are getting the hello world message then you must have run make hello at some stage. Substitute make boot instead.

PS Be sure to include the version of lowRISC you are working with in the subject line.

Sent from my iPhone

On 19 Mar 2018, at 07:58, xubaqian notifications@github.com wrote:

emmm... I generate bitstream, bbl vmlinux and root.bin successfully. Run spike +disk=busybox-1.21.1/root.bin bbl linux-3.14.41/vmlinux I can see linux boots. Copy bbl vmlinux and root.bin to SD card and rename bbl as boot. Download the bitstream to VC707 and I seeHello, World !on terminal but without linux boots. What's wrong ?

Another question is when make boot in vc707 directory, it shows /bin/bash: data2mem: not found, but I have already export XILINX_VIVADO variable and add it to path.

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[wanming2008]

1：i have a vc707 how can i use lowrisc on vc707 board 。 2：do lowrisc support Arty A7-100T？ digilent say A7-100T is same board with nexy4 DDR board？

[jrrk]

Dear Wanming,

We have no access to a VC707 board and no plans to support it. However you can carry out the porting work yourself,

by copying the fpga/board/nexsy4_ddr directory and changing the chip_top.sv in src/main/verilog as well as fpga/board/nexsy4_ddr/scripts/make_project.tcl

and fpga/board/nexsy4_ddr/constraints/pin_plan.xdc. Then you will need to remove or adapt any peripherals that are missing or different on the VC707.

This latter stage will probably take the longest.

On the Arty A7-100T I have better news, you can start with the artya7_mii branch and most of the work is done for you. Bear in mind this board does

not have an SD-card, but operation with an NFSroot or PMOD SD adaptor is theoretically possible.

In almost every case the boards have different Ethernet PHYs or connectivity (MII, GMII, RGMII, XGMII etc). There is little distinction between Kintex and Artix

for your purposes so having exactly the same FPGA is only a small benefit. Of course there is no way one FPGA image can support multiple boards because

there are so many pinout variations.

On 17/01/2019 10:13, WANMING wrote:

1：i have a vc707 how can i use lowrisc on vc707 board 。 2：do lowrisc support Arty A7-100T？ digilent say A7-100T is same board with nexy4 DDR board？

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[hakrdinesh]

Hi,

If you want a RISC-V system right away on your VC707, you can get Sifive Freedom Unleashed 500 platform on it.

It works well. Verified it on a VC707.

If you don't have the additional FMC hardware, you can still run a slightly reconfigured Linux kernel.

Regards, Dinesh

On Thu, Jan 17, 2019, 15:43 WANMING <notifications@github.com wrote:

1：i have a vc707 how can i use lowrisc on vc707 board 。 2：do lowrisc support Arty A7-100T？ digilent say A7-100T is same board with nexy4 DDR board？

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[wanming2008]

Dear Wanming, We have no access to a VC707 board and no plans to support it. However you can carry out the porting work yourself, by copying the fpga/board/nexsy4_ddr directory and changing the chip_top.sv in src/main/verilog as well as fpga/board/nexsy4_ddr/scripts/make_project.tcl and fpga/board/nexsy4_ddr/constraints/pin_plan.xdc. Then you will need to remove or adapt any peripherals that are missing or different on the VC707. This latter stage will probably take the longest. On the Arty A7-100T I have better news, you can start with the artya7_mii branch and most of the work is done for you. Bear in mind this board does not have an SD-card, but operation with an NFSroot or PMOD SD adaptor is theoretically possible. In almost every case the boards have different Ethernet PHYs or connectivity (MII, GMII, RGMII, XGMII etc). There is little distinction between Kintex and Artix for your purposes so having exactly the same FPGA is only a small benefit. Of course there is no way one FPGA image can support multiple boards because there are so many pinout variations. … On 17/01/2019 10:13, WANMING wrote: 1：i have a vc707 how can i use lowrisc on vc707 board 。 2：do lowrisc support Arty A7-100T？ digilent say A7-100T is same board with nexy4 DDR board？ — You are receiving this because you commented. Reply to this email directly, view it on GitHub <#63 (comment)>, or mute the thread https://github.com/notifications/unsubscribe-auth/AAgF12heM2AGG_WWhbW8U4m0_kfjilLmks5vEEzhgaJpZM4O0Mn7.

hi jrrk thank you very much i will buy one nexy4-ddr it seems easier。