Merge upstream Rocket-Chip to support Chisel3+TileLink2+Diplomacy+PLIC-Debug [WIP]

[wsong83]

TODO list:

• [x] clean up a branch
• [x] set up the initial lowrisc-chip chisel top for make
• [x] make our own Node to allow attaching parameters (virtual slaves) but without connect bundles.
• [x] reimplement trait HasMasterAXI4MMIOPort to allow configuration time expansion of multiple slaves to the AXI4SlaveParameters.
• [x] figure out how to add device tree information.
• [x] support interrupt lines for virtual slaves
• [x] bump riscv-tools
• [x] rewrite the SV tope-level
• [x] modify bootrom
• [x] temporarily mute run-control debugger by using a dummy SimDTM
• [x] pass isa regression
• [ ] revise the bare-metal tests
• [ ] test for interrupts
• [ ] find out how to utilize the run-control debugger

Notes:

• Directly attaching virtual peripherals to a AXI master port is a dead end. The AXI parameter is lack of the capability to describe multiple devices! Only TileLink parameters are fully fledged.

[wsong83]

pass ISA regression in both vcs and vsim. Branch merge becomes update.

[asb]

Congratulations Wei! This a fantastic milestone.

[wsong83]

Currently the uart bare-metal test simulated OK. Right now I am going to test it with the real Nexys4-DDR board.

Some inconvenient findings during the process:

• The latest rocket-chip cannot be simulated using Vivado 2015.4, or even any version lower than 2017. The SystemBus module would crash the xelab causing segment error.
• Using Vivado 2017.3, I can run simulation. However, the DPI interface somehow does not work yet (I was forced to disable all DPI calls to avoid run-time exceptions) also the synthesis will crash without a reason.

That is to say, there is current NO stable version of Vivado that can do implementation and simulation at the same time.

For the sake of debugging, I leave the simulatible version in a branch called vivado-2017.3 of the lowrisc-nexys4 repo.

[wsong83]

Close this issue for now.