Update lowRISC with the upstream Rocket-chip [WIP]

lowRISC / lowrisc-chip

The root repo for lowRISC project and FPGA demos.

http://www.lowrisc.org/

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Update lowRISC with the upstream Rocket-chip [WIP] #73

Closed wsong83 closed 7 years ago

wsong83 commented 7 years ago

Use the upstream Rocket-Chip.
Extend Rocket-Chip to support SV top-level interconnects with parameter and interrupts back-propagation.
Rewrite top SV.
Pass ISA regression again.

Once the ISA regression is passed, this will be merged to branch update.

wsong83 commented 7 years ago

Merged.

ATTN: There seems to be some bugs in the Verilator. With or without the --trace argument changes the internal scheduling of the generated C++ simulator (with the same Chisel generated Verilog). I do not have enough time to dig deep enough to understand what exactly is the problem. Right now I add the --trace argument for normal isa regression passes. Simulation time is not changed much but Verilator compilation time increases more than doubled.