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lowRISC / lowrisc-chip

The root repo for lowRISC project and FPGA demos.
http://www.lowrisc.org/
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BlackBox #78

Closed clare7 closed 7 years ago

clare7 commented 7 years ago

Would it be possible to use the blackbox for Verilog integration (such as BlackBoxInline, BlackBoxResource utility from Chisel 3) in this version of LowRiscv chip? If not any advice or alternative that could work for this chip?

wsong83 commented 7 years ago

We do use blackbox for the trace debugger, see this one for an example: https://github.com/opensocdebug/hardware/blob/master/modules/ctm/riscv/rocket/ctm.scala

However, all the released lowRISC versions use Chisel 2 rather than Chisel 3, so the blackbox utilities mentioned in your questions are not available. Hopefully lowRISC will migrate to Chisel 3 soon (which is in the plan).

clare7 commented 7 years ago

Thanks! manage to get my code works. Also found another useful reference: https://groups.google.com/a/groups.riscv.org/forum/#!topic/hw-dev/7ztcExvdGFM