lowRISC / lowrisc-chip

The root repo for lowRISC project and FPGA demos.
http://www.lowrisc.org/
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Can I ask you a question about the simulation? #80

Closed thecakim closed 6 years ago

thecakim commented 6 years ago

Hello I am a student studying computer architecture.

I would like to customize the lowRISC chip to apply in my ideas. I have trouble in checking the simulation results and understanding the entire structure. so..I need your help.. TT

  1. The $ TOP / src / main directory contains the 'verilog' and 'scala' directories. I wonder if they both describe the same thing. When I create a bitstream or simulator, I see only .sv(verilog) in the Makefile (which I may have misunderstood). So what should I do to fix the verilog? Does not the chisel need to be modified?

  2. To check the operation of lowRISCV-chip with waveform http://www.lowrisc.org/docs/untether-v0.2/vsim/ I proceeded as follows:

cd $ TOP / vsim make sim-debug elf2hex 16 4096 rv64ui-p-add> rv64ui-p-add.hex

As a result of executing the third command, the following statement appears.

_Assertion `fd! = -1 'failed. If you do not want to use std :: basic_string, you can use std :: basic_string with a long unsigned int> load_elf (const char , memif_t )_

Is there a way to solve this problem and see the motion waveform of rv64ui-p-add? hlep me .. plz