NastiIO bus width

[clare7]

For this version, would it be possible to change the bus width size of mem_nasti interface with the memory controller from 64 to 128 bits?

For instance, changing 64 to 128 below:

 <AXIParameters>
            <C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
            <C0_S_AXI_ADDR_WIDTH>30</C0_S_AXI_ADDR_WIDTH>
            <C0_S_AXI_DATA_WIDTH>64</C0_S_AXI_DATA_WIDTH>
            <C0_S_AXI_ID_WIDTH>4</C0_S_AXI_ID_WIDTH>
            <C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>
        </AXIParameters>

[wsong83]

Yes, if you also tweak the clock rate and the data width of the axi_clock_converter.

[clare7]

Noted. but I'm not so sure about the clock rate. I use the following but it doesnt work:

# AXI clock converter due to the clock difference
create_ip -name axi_clock_converter -vendor xilinx.com -library ip -version 2.1 -module_name axi_clock_converter_0
set_property -dict [list \
                        CONFIG.ADDR_WIDTH {30} \
                        CONFIG.DATA_WIDTH $mem_data_width \
                        CONFIG.ID_WIDTH $aximm_id_width \
                        CONFIG.ACLK_ASYNC {1} \
                        CONFIG.SYNCHRONIZATION_STAGES {4}] \
    [get_ips axi_clock_converter_0]
generate_target {instantiation_template} [get_files $proj_dir/$project_name.srcs/sources_1/ip/axi_clock_converter_0/axi_clock_converter_0.xci]

My intention is to only set the nasti bus between L2 and MC to the width of 128.

[wsong83]

No idea about how it does not work but I am no longer in a position to support this old version anyway. If what you want is to increase the bandwidth between L2 and MC, which includes increasing the data width of the L2 outer ports, this is not easy. The TileLink in this version is tricky. I do not think you want to touch it. For the current problem, what I can suggest is to run a simulation and see why it does not work.

[jrrk]

Dear Clare, If you update to the latest Rocket (kc705_mii branch), there is no L2 but the L1 data width may be set in the Chisel code with the beatbytes parameter and likewise the clock_converter width and DDR controller width config also needs changing. I am not aware that the clock rate would change in this version. As Wei says it all needs re-verifying in simulation.

Regards, Jonathan

Sent from my iPhone

On 19 Nov 2018, at 07:28, Wei Song (宋威) notifications@github.com wrote:

No idea about how it does not work but I am no longer in a position to support this old version anyway. If what you want is to increase the bandwidth between L2 and MC, which includes increasing the data width of the L2 outer ports, this is not easy. The TileLink in this version is tricky. I do not think you want to touch it. For the current problem, what I can suggest is to run a simulation and see why it does not work.

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[clare7]

When I try to boot the Linux (boot.bin)

I have the following error:

elf read failed with code Boot the loaded program...
mcause=2
mepc=80000010
mbadaddr=80000010
einsn=aaaaaaaa
sp=4000f978
tp=4000cb00
error! exit(0x0000000000000539)

any idea/advice what might have gone wrong?

[jrrk]

As previously stated by Wei, you need to get the simulation up and running and check the waveforms.

And of course in any bug report, reconfirm what version you are using and what you have changed.

Pay particular attention in the simulation to any startup messages referring to mismatched widths.

On 19/11/2018 08:16, clare7 wrote:

When I try to boot the Linux (boot.bin)

I have the following error:

|elf read failed with code Boot the loaded program... mcause=2 mepc=80000010 mbadaddr=80000010 einsn=aaaaaaaa sp=4000f978 tp=4000cb00 error! exit(0x0000000000000539) |

any idea/advice what might have gone wrong?

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