[bazel, sca] Ensure that englishbreakfast CI builds can use Bazel to build their SW artifacts.

[mcy]

See https://github.com/lowRISC/opentitan/pull/12083, which enables doing this (but does not turn it on in CI).

I don't understand what SCA CI is doing, so I would appreciate guidance here, @vogelpi

[vogelpi]

Hey @mcy , for English Breakfast, we just run the AES smoketest in Verilator and build the FPGA bitstream. The smoketest is primarily used to capture cases where English Breakfast doesn't boot, e.g., because of issues in the modified test ROM or the hardware itself.

We can't run aes_serial (and sha3_serial Earl Grey only) doing the actual power trace capture as this would require us to connect more FPGA boards and modify the CI setup (different Python dependencies). So when you edit/move these over to Bazel please let me, @andreaskurth and @vrozic know such that we can have a quick look and verify that stuff keeps working on the actual FPGA.

[moidx]

Hi @vogelpi, is there additional work needed here?

[vogelpi]

My understanding is that all the required work has been done.

In CI, we build the SW artifacts for English Breakfast using ci/scripts/run-english-breakfast-verilator-tests.sh which under the hood calls ./hw/top_englishbreakfast/util/prepare_sw.py -b to patch the SW tree and build SW artifacts using Bazel. The tests are then run via opentitantool.

The actual Verilator simulation is not built via Bazel but instead using ci/scripts/build-chip-verilator.sh englishbreakfast. But I think changing this wasn't in scope for this issue anyway. I am thus closing it.