[chip-test] (DV-only) chip_sw_spi_device_pass_through_flash_model

[weicaiyang]

Test point name

chip_sw_spi_device_pass_through_flash_model

Host side component

SystemVerilog+Rust

OpenTitanTool infrastructure implemented

Unknown

Contact person

@eunchan

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

• [ ] Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
• [ ] Device-side (C) component developed
• [ ] Bazel build rules developed
• [ ] Host-side component developed
• [ ] HJSON test plan updated with test name (so it shows up in the dashboard)
• [ ] Test added to dvsim nightly regression (and passing at time of checking)

[tjaychen]

since the actual instantiation of the flash model has been pushed to M3, it seems only reasonable to push this test to M3 as well. @a-will / @weicaiyang let me know disagree, I'll make the change first.

[weicaiyang]

since the actual instantiation of the flash model has been pushed to M3, it seems only reasonable to push this test to M3 as well. @a-will / @weicaiyang let me know disagree, I'll make the change first.

oh, I mentioned we need to postpone this test in a PR too, but I forgot to update this issue. Thanks for the update.

[tjaychen]

thanks for confirming @weicaiyang !

[tjaychen]

i think similar to the windbond bfm thing... we probably are going to actually do this on fpga right? so maybe it's best to move to backlog?

[weicaiyang]

Perhaps P4 for now? If we find a good flash model, we can still do it.

[tjaychen]

sounds good to me.

[andreaskurth]

Triated for spi_device. The current plan for verifying spi_host with a flash as part of M2.5 is in #15074. This issue can then leverage that to connect spi_device in passthrough mode. I'm thus assigning this to M2.5 with https://github.com/lowRISC/opentitan/labels/Priority%3AP2.

[hcallahan-lowrisc]

estimate 8 remaining 2023-03-22 8

[moidx]

Updating label to Priority:P4 as there is no current plan to integrate SPI EEPROM model in DV due to the lack of model availability. The current approach relies on FPGA testing.

[andreaskurth]

Updating label to Priority:P4 as there is no current plan to integrate SPI EEPROM model in DV due to the lack of model availability. The current approach relies on FPGA testing.

Are we sure about P4'ing this? This issue currently tracks testing SPI passthrough with a flash in general, not specifically using a model for the flash, right? Or do we have a separate issue that tracks testing SPI passthrough with a flash chip? If not, I would keep P2 (and maybe rename the test to remove the _model suffix).

[moidx]

Hi @andreaskurth, I agree that if we refactor this issue to remove the model part, we can make it a P2. Otherwise we need to create a separate issue. Thanks

[moidx]

Discussed offline with @johngt and decided to track FPGA work on a separate issue. @hcallahan-lowrisc to cross link the issue.

[hcallahan-lowrisc]

https://github.com/lowRISC/opentitan/issues/13484 https://github.com/lowRISC/opentitan/issues/17782

[johngt]

@a-will - this is most likely irrelevant as it has been superseded now and can be closed out? @msfschaffner

[a-will]

@johngt This issue seems to be in a terminal state of, "Would be nice, but will never actually happen." I think we could at least consider closing this as not planned.

[engdoreis]

Closing in favour of https://github.com/lowRISC/opentitan/issues/20633

[a-will]

This issue is purely about DV and using a real SPI flash verification model. Reopening, since we haven't all agreed to close yet.

Please don't mistake this for a silicon validation or FPGA issue. Those are covered by the other testplan items that don't end in _model, as a real SPI flash device is integral to testing on those platforms.

[a-will]

Blocked until we actually have a verification model.