lowRISC / opentitan

OpenTitan: Open source silicon root of trust
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[test-triage] chip_jtag_mem_access #14195

Closed jdonjdon closed 2 years ago

jdonjdon commented 2 years ago

Hierarchy of regression failure

Chip Level

Failure Description

  Offending '(dmem_rdata_bus == 'b0)'

UVM_ERROR @ 9128.296472 us: (otbn.sv:1217) [ASSERT FAILED] NonIdleDmemReadsZero_A

Steps to Reproduce

GH revision: 9c0b24ddb util/dvsim/dvsim.py hw/top_earlgrey/dv/chip_sim_cfg.hjson -i chip_jtag_mem_access --build-seed 2483310614 --fixed-seed 581187855

Tests with similar or related failures

No response

tjaychen commented 2 years ago

related to #14066