The topearlgrey XBAR block level as well as the full chip level use the generated `xbar*_bindSV files which bind thetlul_assert` instances to all hosts and devices.
The associated fusesoc core is named lowrisc:dv:xbar_main_bind, lowrisc:dv:xbar_peri_bind.
These sources are generated for top_englishbreakfast as well. Ideally they should not have been generated for this top, because it does not have any DV environment - it is only used with Verilator and FPGA.
Since we set our fusesoc root search path to our repo root, this causes a namespace collision - both top-specific versions have the same fusesoc core name. In some cases, I have run into a situation where the DV simulation for top_earlgrey ends up picking up the xbar bind sources generated for englishbreakfast.
While this is an easy fix, I am filing an issue since there may be other top specific generated sources that also need disambiguation, fusesoc core name wise. Eventually, this will need to be enforced as a methodology guideline.
The topearlgrey XBAR block level as well as the full chip level use the generated `xbar*_bind
SV files which bind the
tlul_assert` instances to all hosts and devices.The associated fusesoc core is named
lowrisc:dv:xbar_main_bind
,lowrisc:dv:xbar_peri_bind
.These sources are generated for
top_englishbreakfast
as well. Ideally they should not have been generated for this top, because it does not have any DV environment - it is only used with Verilator and FPGA.Since we set our fusesoc root search path to our repo root, this causes a namespace collision - both top-specific versions have the same fusesoc core name. In some cases, I have run into a situation where the DV simulation for top_earlgrey ends up picking up the xbar bind sources generated for englishbreakfast.
While this is an easy fix, I am filing an issue since there may be other top specific generated sources that also need disambiguation, fusesoc core name wise. Eventually, this will need to be enforced as a methodology guideline.