[test-triage] chip_sw_sleep_pin_retention

johngt commented 2 years ago

Hierarchy of regression failure

Chip Level

Failure Description

UVM_ERROR @ * us: (sw_test_status_if.sv:75) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] ==== SW TEST FAILED ==== has 3 failures:

Test chip_sw_sleep_pin_retention has 3 failures.
0.chip_sw_sleep_pin_retention.3780831391
Line 488, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  UVM_ERROR @ 3125.496616 us: (sw_test_status_if.sv:75) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] ==== SW TEST FAILED ====
  UVM_INFO @ 3125.496616 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_sleep_pin_retention.187093644
Line 485, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_sleep_pin_retention/latest/run.log

  UVM_ERROR @ 3152.548666 us: (sw_test_status_if.sv:75) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] ==== SW TEST FAILED ====
  UVM_INFO @ 3152.548666 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Steps to Reproduce

Commit hash where failure was observed: c2a8c64cc
dvsim invocation command to reproduce the failure, inclusive of build and run seeds: ./util/dvsim/dvsim.py hw/top_earlgrey/dv/chip_sim_cfg.hjson -i chip_sw_sleep_pin_retention --fixed-seed 3780831391 --build-seed 4265629825 --waves -v h
If dvsim invocation is incorrect - test is chip_sw_sleep_pin_retention

Test has only existed across this weekend. May be resolved by original developer. Observe for now

Tests with similar or related failures

[ ] chip_sw_sleep_pin_retention
[ ] Unmapped tests

engdoreis commented 2 years ago

It relates to #14352, and it will probably be tackled there.

eunchan commented 2 years ago

I don't know why this one is included in the regression. Anyway, the test is not 100% implemented and failure is expected. I will update this Issue when I implement it.

engdoreis commented 2 years ago

Thanks @eunchan.

cindychip commented 2 years ago

@eunchan looks like this test is passing now? Can we close this issue?

eunchan commented 2 years ago

PR #15421 should be merged before closing this.

lowRISC / opentitan