[test-triage] chip_sw_clkmgr_escalation_reset

cindychip commented 2 years ago

Hierarchy of regression failure

Chip Level

Failure Description

UVM_ERROR @ 3383.073776 us: (cip_base_scoreboard.sv:436) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@140559) { a_addr: 'h1001fe7c a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1 a_opcode: 'h4 a_user: 'h272aa d_param: 'h0 d_source: 'h1 d_data: 'hffffffff d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'heaa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 } , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0 UVM_INFO @ 3383.073776 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---

Steps to Reproduce

Commit hash: https://github.com/lowrisc/opentitan/tree/84fdd3bf374f168367ba7ffcb07cfa4d79c54875
dvsim invocation command to reproduce the failure, inclusive of build and run seeds: ./util/dvsim/dvsim.py hw/top_earlgrey/dv/chip_sim_cfg.hjson -i chip_sw_clkmgr_escalation_reset --fixed-seed 4097340474 --build-seed 2438508852 --waves -v h

Tests with similar or related failures

No response

tjaychen commented 2 years ago

re-open just to double check.

tjaychen commented 2 years ago

this has also passed local runs of 10+. Closing it down now.

lowRISC / opentitan