[test-triage] chip_sw_sram_ctrl_execution_main

[cindychip]

Hierarchy of regression failure

Chip Level

Failure Description

UVM_ERROR @ 3771.762672 us: (sw_logger_if.sv:522) [sram_ctrl_execution_test_main_prog_sim_dv(sw/device/tests/sim_dv/sram_ctrl_execution_test_main.c:183)] CHECK-fail: Expected exception not observed whilst executing from SRAM! UVM_INFO @ 3771.762672 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---

Steps to Reproduce

• Commit hash: https://github.com/lowrisc/opentitan/tree/84fdd3bf374f168367ba7ffcb07cfa4d79c54875
• dvsim invocation command to reproduce the failure, inclusive of build and run seeds: ./util/dvsim/dvsim.py hw/top_earlgrey/dv/chip_sim_cfg.hjson -i chip_sw_sram_ctrl_execution_main --fixed-seed 1010556540 --build-seed 2438508852 --waves -v h

Tests with similar or related failures

No response

[tjaychen]

fix in #15583