[chip-test] chip_sw_lc_ctrl_kmac_error

[sriyerg]

Test point name

chip_sw_lc_ctrl_kmac_error

Host side component

SystemVerilog / Rust

OpenTitanTool infrastructure implemented

Yes

Silicon Validation (SiVal)

Yes

Emulation targets

• [ ] None
• [ ] CW310
• [ ] Hyperdebug + CW310

Contact person

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

• [ ] Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
• [ ] Device-side (C) component developed
• [ ] Bazel build rules developed
• [ ] Host-side component developed
• [ ] Test added to dvsim nightly regression (and passing at time of checking)
• [ ] For SiVal test cases, test is running relevant FPGA or silicon regression

[moidx]

Reviewed with @cindychip. This has been covered at block level. There is a chip level coverage for the error signal between lc_ctrl and kmac. Alert handler escalations are tested separately for each block.

Lowering the priority as the physical interface between the two components is already covered in many lc_ctrl top level test cases.

[moidx]

Moving V3 tasks to the next Earlgrey release.