[chip-test] chip_sw_keymgr_sideload_kmac_error

[sriyerg]

Test point name

chip_sw_keymgr_sideload_kmac_error

Host side component

SystemVerilog

OpenTitanTool infrastructure implemented

No response

Contact person

@tjaychen, @eunchan, @weicai

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

• [ ] Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
• [ ] Device-side (C) component developed
• [ ] Bazel build rules developed
• [ ] Host-side component developed
• [ ] HJSON test plan updated with test name (so it shows up in the dashboard)
• [ ] Test added to dvsim nightly regression (and passing at time of checking)

[tjaychen]

assigning to @ballifatih and @weicaiyang for now to update the testplan description, since it is left as "TBD" right now for what happens when an error occurs.

[weicaiyang]

assigning to @ballifatih and @weicaiyang for now to update the testplan description, since it is left as "TBD" right now for what happens when an error occurs.

updated in #16661 changing this issue to unassigned

[ballifatih]

I can implement this test, so feel free to re-assign me once we merge the test plan @weicaiyang.

[weicaiyang]

I can implement this test, so feel free to re-assign me once we merge the test plan @weicaiyang.

Thanks @ballifatih

[cindychip]

If M2.5 has enough bandwidth, we can consider this test. Otherwise should be covered in block level for keymgr and kmac.

[msfschaffner]

Deferred to after M2.5 since this is not critical for the mainline functionality.

[vogelpi]

I've lowered the priority here as I believe we wouldn't gain too much from this compared to the required effort for implementing this test (it won't run on silicon due to the required glitching).

[ballifatih]

I was assigned to this issue temporarily long time ago, but I unassigned myself from this issue, as I do not have bandwidth for it.