[chip-test] chip_sw_rom_ctrl_kmac_error

sriyerg commented 2 years ago

Test point name

chip_sw_rom_ctrl_kmac_error

Host side component

SystemVerilog

OpenTitanTool infrastructure implemented

No response

Contact person

@tjaychen, @eunchan, @ctopal

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

[ ] Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
[ ] Device-side (C) component developed
[ ] Bazel build rules developed
[ ] Host-side component developed
[ ] HJSON test plan updated with test name (so it shows up in the dashboard)
[ ] Test added to dvsim nightly regression (and passing at time of checking)

cindychip commented 1 year ago

Best efforts test for M2.5. This error case is covered in block level DV.

vogelpi commented 4 months ago

I've lowered the priority here as I believe we wouldn't gain too much from this compared to the required effort for implementing this test (it won't run on silicon due to the required glitching).

lowRISC / opentitan