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lowRISC / opentitan

OpenTitan: Open source silicon root of trust
https://www.opentitan.org
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[csrng] csrng_internal_cg implementation #16201

Closed marnovandermaas closed 1 year ago

marnovandermaas commented 1 year ago

Based on the changes to the test plan proposed in: https://github.com/lowRISC/opentitan/pull/16116

We need an extra cover group to create coverage on the internal state of the CSRNG block.

Old estimate before 2022-11-11 8

estimate 16 remaining 2022-11-11 8 remaining 2022-11-12 2

marnovandermaas commented 1 year ago

I've added an initial implementation on the internal cover group, but am struggling with how to implement the sampling.

spent 8 remaining 2022-11-11 8

vogelpi commented 1 year ago

genbits (can see that from toggle coverage), genbits_v, sw_cmd_status, intr_state, intr_en - to sample on every clock edge, Andreas shared an example

marnovandermaas commented 1 year ago

We decided this issue can be roped into https://github.com/lowRISC/opentitan/issues/15742 I opened a draft PR (very incomplete) as a reference for what I did so far: https://github.com/lowRISC/opentitan/pull/16254

vogelpi commented 1 year ago

Thanks @marnovandermaas , this is helpful. I am un-assigning you for the moment to let you work on the V2S task as just discussed.

ctopal commented 1 year ago

Okay, I think I'll just use the scoreboard more effectively to sample interrupt related covergroups that gets generated from cip_base_env_cov. For other coverpoints, I believe adding them to err_cg would be sufficient.

ctopal commented 1 year ago

List of things written down in https://github.com/lowRISC/opentitan/pull/16116: