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OpenTitan: Open source silicon root of trust
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[chip-test] chip_sw_tap_strap_sampling #16834

Open sriyerg opened 1 year ago

sriyerg commented 1 year ago

Test point name

chip_sw_tap_strap_sampling

Host side component

SystemVerilog

OpenTitanTool infrastructure implemented

None

Contact person

sriyerg

Checklist

This test is already developed. This issue tracks the effort to enhance it for V3. The pending work item is referenced in the link to the testplan above:

 Verify loss of DFT functionality when DFT straps are deasserted on the next POR cycle.
andreaskurth commented 5 days ago

This is a V3 item, so I'm proposing to move it to M7