Open marnovandermaas opened 1 year ago
@GregAC , thanks for looking into this. I looked at the pinout and IOs specification and it seems that the IOs which Google have designated for I2C have internal 50ns glitch suppression filter (hard wired) and a configurable Schmitt trigger option. So, as long as we select those IOs by pin mux and make sure the Schmitt trigger option is activated, we are good.
The pinout is described at: https://opentitan.org/book/hw/top_earlgrey/doc/design/index.html The I2C compatible IO type is BidirOd
Thanks @zi-v.
In which case no changes required here for M2.5. I'll leave this tagged as future release as the proposed spike suppression logic may be useful in other uses of the IP or OpenTitan integratations where the Schmitt Trigger/Glitch suppression filter is not available.
Given that we are using the same pad configuration and pad cells for Earlgrey production silicon, I don't think this change is needed. Putting into the backlog again.
Description
Issue raised by @zi-v and written up by @GregAC