[dv/lc_ctrl] Expanding JTAG registers + multiple address maps

[gdessouky]

Description

• [ ] In lc_ctrl_scoreboard.sv https://cs.opensource.google/opentitan/opentitan/+/master:hw/ip/lc_ctrl/dv/env/lc_ctrl_scoreboard.sv ambiguous TODO on expanding for JTAG registers, iceboxed with ref to this issue # until we figure out what it means
• [ ] In lc_ctrl_env_cfg.sv https://cs.opensource.google/opentitan/opentitan/+/master:hw/ip/lc_ctrl/dv/env/lc_ctrl_env_cfg.sv another ambiguous TODO on using multiple address maps for JTAG for register accesses, iceboxed with ref to this issue # until we figure out what it means

[rswarbrick]

I just had a look at the TODO comments that this tracked. For the second item (in lc_ctrl_env_cfg.sv), I looked at the commit that added the TODO (517c1577431).

I think the "multiple address maps" text refers to the fact that we've cloned a UVM address map in post_build_ral_settings, giving us a second copy that represents the fact we can talk to registers over either TL or JTAG. The jtag_csr bit is supposed to be a flag that tells the DV environment to get into a mode where it uses JTAG for accesses (switching in end_of_elaboration_phase). The TODO comment is a reminder that maybe we should test this! Doing so might be as simple as randomising jtag_csr in the build phase for lc_ctrl_base_test instead of looking at a plusarg.

Probably not urgent enough for a project milestone though.

I couldn't figure out the first item, but we would probably need to spend an hour thinking before dropping it.

[rswarbrick]

I still believe that this is low priority (V3 at most) and probably doesn't need to be handled for M5. Tagging as a triage priority accordingly.

[rswarbrick]

Moving to M7, where we plan to target V3 status.

[moidx]

lc_ctrl V3 moved to next Earlgrey release.