[spi_device,dv] Add assertion to test SRAM logic is faster than update of current_address_i.

[hcallahan-lowrisc]

Description

https://github.com/lowRISC/opentitan/blob/39f9a9e57286f0d2a72c624bb19b9bd3a4c3bdf0/hw/ip/spi_device/rtl/spid_readsram.sv#L274-L277

[moidx]

@antmarzam, @hcallahan-lowrisc, if the design assumption is not correct, we expect to see failures at block and top level as long as we are randomizing the contents of SRAM (per address). Can you take a look and move to M7 if this is the case?

AI: Check for pre-existing GitHub issues to see if this is covered elsewhere.

[andreaskurth]

Quoting @hcallahan-lowrisc (out of band communication):

we discussed in the review meeting that if this condition was not true then there would be wide breakage across the whole project. As such, decided that low priority/ M7 is fine.

Just discussed in issue triage that we agree and hence move this to M7.