sw/device/silicon_creator/rom/e2e/boot_policy_bad_manifest_too_small_b_img_sim_verilator errors out in verilator

[alphan]

[2023-05-12T08:54:48Z INFO  opentitanlib::transport::verilator::subprocess::stdout] Simulation of OpenTitan Earl Grey
[2023-05-12T08:54:48Z INFO  opentitanlib::transport::verilator::subprocess::stdout] 
[2023-05-12T08:54:48Z INFO  opentitanlib::transport::verilator::subprocess::stdout] =================================
[2023-05-12T08:54:48Z INFO  opentitanlib::transport::verilator::subprocess::stdout] 
[2023-05-12T08:54:48Z INFO  opentitanlib::transport::verilator::subprocess::stdout] 
[2023-05-12T08:54:48Z INFO  opentitanlib::transport::verilator::subprocess::stdout] 
[2023-05-12T08:54:48Z INFO  opentitanlib::transport::verilator::subprocess::stdout] %Error: sw/device/silicon_creator/rom/e2e/boot_policy_bad_manifest_too_small_b_img_sim_verilator.signed.64.scr.vmem:16384: $readmem file address beyond bounds of array
[2023-05-12T08:54:48Z INFO  opentitanlib::transport::verilator::subprocess::stdout] 
[2023-05-12T08:54:48Z INFO  opentitanlib::transport::verilator::subprocess::stdout] Aborting...
[2023-05-12T08:54:48Z INFO  opentitanlib::transport::verilator::subprocess::stdout] 
Error: Timed out

Stack backtrace:
   0: anyhow::error::<impl anyhow::Error>::msg
   1: anyhow::__private::format_err
   2: opentitanlib::transport::verilator::subprocess::Subprocess::find
   3: opentitanlib::transport::verilator::transport::Verilator::from_options
   4: opentitanlib::backend::verilator::create
   5: opentitanlib::backend::create
   6: opentitantool::main
   7: core::ops::function::FnOnce::call_once
   8: std::sys_common::backtrace::__rust_begin_short_backtrace
   9: std::rt::lang_start::{{closure}}
  10: core::ops::function::impls::<impl core::ops::function::FnOnce<A> for &F>::call_once
             at /rustc/c18a5e8a5b1afb0d7a582fe9ebad4c1996c90da3/library/core/src/ops/function.rs:287:13
  11: std::panicking::try::do_call
             at /rustc/c18a5e8a5b1afb0d7a582fe9ebad4c1996c90da3/library/std/src/panicking.rs:483:40
  12: std::panicking::try
             at /rustc/c18a5e8a5b1afb0d7a582fe9ebad4c1996c90da3/library/std/src/panicking.rs:447:19
  13: std::panic::catch_unwind
             at /rustc/c18a5e8a5b1afb0d7a582fe9ebad4c1996c90da3/library/std/src/panic.rs:140:14
  14: std::rt::lang_start_internal::{{closure}}
             at /rustc/c18a5e8a5b1afb0d7a582fe9ebad4c1996c90da3/library/std/src/rt.rs:148:48
  15: std::panicking::try::do_call
             at /rustc/c18a5e8a5b1afb0d7a582fe9ebad4c1996c90da3/library/std/src/panicking.rs:483:40
  16: std::panicking::try
             at /rustc/c18a5e8a5b1afb0d7a582fe9ebad4c1996c90da3/library/std/src/panicking.rs:447:19
  17: std::panic::catch_unwind
             at /rustc/c18a5e8a5b1afb0d7a582fe9ebad4c1996c90da3/library/std/src/panic.rs:140:14
  18: std::rt::lang_start_internal
             at /rustc/c18a5e8a5b1afb0d7a582fe9ebad4c1996c90da3/library/std/src/rt.rs:148:20
  19: std::rt::lang_start
  20: main
  21: __libc_start_main
  22: <unknown>```

[Slack Message](https://opentitan.slack.com/archives/D054V4YQ495/p1684052124225599)

[a-will]

In case it's relevant, the Verilator simulation flow doesn't support the second bank of flash yet in some contexts: https://github.com/lowRISC/opentitan/blob/3d5660d90142eab4158eb1ed5285415ca01b3f39/hw/top_earlgrey/dv/verilator/chip_sim_tb.cc#L34

I never got around to finishing code to create a virtual target that spans multiple banks, heh.

[alphan]

In case it's relevant, the Verilator simulation flow doesn't support the second bank of flash yet in some contexts: https://github.com/lowRISC/opentitan/blob/3d5660d90142eab4158eb1ed5285415ca01b3f39/hw/top_earlgrey/dv/verilator/chip_sim_tb.cc#L34

I never got around to finishing code to create a virtual target that spans multiple banks, heh.

Thanks @a-will ! Most likely that's the root cause. I can take a look at this but probably will need your input.

[dbeitel-opentitan]

Is there a subset of bazel tests that run successfully?

[a-will]

With #18870 merged, we now have the ability to cover the whole flash with VMEM files for the Verilated simulator.

We still need to add bazel support for splitting the large binary into appropriately-targeted VMEM files, then specifying the banks to opentitantool.

[moidx]

Verilator is not part of the sign-off criteria for Earlgrey-PROD. Moving to backlog.