[test-triage] uart_rx_oversample

[johngt]

Hierarchy of regression failure

Block level

Failure Description

  UVM_ERROR @ 656811645 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (23012 [0x59e4] vs 46024 [0xb3c8]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @ 665361278 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 4/6
  UVM_ERROR @ 665478381 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (31719 [0x7be7] vs 63439 [0xf7cf]) Regname: uart_reg_block.val.rx reset value: 0x0
  UVM_INFO @ 882020061 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 5/6
  UVM_INFO @ 1201077341 ps: (uart_rx_oversample_vseq.sv:37) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_oversample_vseq] finished run 6/6

84%

Steps to Reproduce

• GitHub Revision: 50278df8b
• dvsim invocation command to reproduce the failure, inclusive of build and run seeds: ./util/dvsim/dvsim.py hw/top_earlgrey/dv/chip_sim_cfg.hjson -i uart_rx_oversample --build-seed 1341560578 --fixed-seed 3644022023 --waves fsdb

Tests with similar or related failures

• [ ] rx_oversample

[msfschaffner]

Discussed in the triage meeting - moving to V3 as a coverage closure task.

[johngt]

Worth @GregAC looking into this and seeing if this is still an issue or not. If no longer relevant can close out, otherwise should check priority and milestone. @moidx

[rswarbrick]

As this is a V3 issue, I'm moving this to the M7 milestone.