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[dvsim/dc] Macro `ASSERT_KNOWN matchs the definition is failure #19361

Open gzyangcs opened 11 months ago

gzyangcs commented 11 months ago

Description

Hello sir, i want to inject some faults into AES with tool synfi which needs netlist, so i tried to synthsis IP AES with tool dc, the command is below: opentitan/hw/ip/aes/syn$ dvsim ./aes_gtech_syn_cfg.hjson --purge --local

then, errors encountered! The build.log shows that error happens at command analyze -vcs "-sverilog +define+${DEFINE} -f ${SV_FLIST}" > "${REPDIR}/analyze.rpt"

When i check analyze.rpt, it notes me that "Error: ../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv:141: The number of parameters for the 'ASSERT_KNOWN' macro doesn't match its definition. (VER-927)".

The problem is i did not chage any RTL & hjson, and i did't found problems when check the define ASSERT_KNOWN.

The ASSERT_KNOWN defined at prim_assert_standard_macros.svh is 

`define ASSERT_KNOWN(__name, __sig, __clk = `ASSERT_DEFAULT_CLK, __rst = `ASSERT_DEFAULT_RST) \
  `ASSERT(__name, !$isunknown(__sig), __clk, __rst)

The ASSERT_KNOWN called at prim_arbiter_fixed.sv:141 is 

  `ASSERT_KNOWN(ValidKnown_A, valid_o)
  `ASSERT_KNOWN(GrantKnown_A, gnt_o)
  `ASSERT_KNOWN(IdxKnown_A, idx_o)

But, it is fine if change ASSERT_KNOWN(ValidKnown_A, valid_o) to ASSERT_KNOWN(ValidKnown_A, valid_o, clk_i, !rst_ni).

And, the same error when i synthesis other IPs like lc_ctrl. So what can i do next?

Your help would be greatly appreciated.

Enviroment

OS: Ubuntu 20.04.1 LTS Kernel: Linux 5.8.0-38-generic Architecture: x86-64 Opentitan: lastest

Logs

The build.log is below:

[Executing]:
make -f /home/work/test/opentitan/hw/syn/tools/dvsim/syn.mk build build_cmd=dc_shell-xg-t build_dir=/home/work/test/opentitan/scratch/master/aes-syn-dc/default build_log=/home/work/test/opentitan/scratch/master/aes-syn-dc/default/synthesis.log build_opts='-f /home/work/test/opentitan/hw/syn/tools/dc/run-syn.tcl' build_timeout_mins=None post_build_cmds='' pre_build_cmds='' proj_root=/home/work/test/opentitan report_cmd=/home/work/test/opentitan/hw/syn/tools/dc/parse-syn-report.py report_opts='--dut aes --expand-modules aes --expand-depth 1 --log-path /home/work/test/opentitan/scratch/master/aes-syn-dc/default --rep-path /home/work/test/opentitan/scratch/master/aes-syn-dc/default/REPORTS --out-dir /home/work/test/opentitan/scratch/master/aes-syn-dc/default --termination-stage compile' sv_flist_gen_cmd=fusesoc sv_flist_gen_dir=/home/work/test/opentitan/scratch/master/aes-syn-dc/default/syn-icarus sv_flist_gen_opts='--cores-root /home/work/test/opentitan run --flag=fileset_ip --target=syn --tool icarus --build-root=/home/work/test/opentitan/scratch/master/aes-syn-dc/default --setup lowrisc:ip:aes:1.0'

[make]: gen_sv_flist
cd /home/work/test/opentitan/scratch/master/aes-syn-dc/default && fusesoc --cores-root /home/work/test/opentitan run --flag=fileset_ip --target=syn --tool icarus --build-root=/home/work/test/opentitan/scratch/master/aes-syn-dc/default --setup lowrisc:ip:aes:1.0
INFO: Preparing lowrisc:constants:top_pkg:0
INFO: Preparing lowrisc:dv:dv_macros:0
INFO: Preparing lowrisc:dv:pins_if:0
INFO: Preparing lowrisc:ip:entropy_src_pkg:0.1
INFO: Preparing lowrisc:prim:assert:0.1
INFO: Preparing lowrisc:prim:cipher_pkg:0.1
INFO: Preparing lowrisc:prim:pad_wrapper_pkg:0
INFO: Preparing lowrisc:prim:primgen:0.1
INFO: Preparing lowrisc:prim:secded:0.1
INFO: Preparing lowrisc:prim:arbiter:0
INFO: Preparing lowrisc:prim:cdc_rand_delay:0
INFO: Preparing lowrisc:prim:cipher:0
INFO: Preparing lowrisc:prim:count:0
INFO: Preparing lowrisc:prim:lfsr:0.1
INFO: Preparing lowrisc:prim:prim_pkg:0.1
INFO: Preparing lowrisc:prim:sec_anchor:0.1
INFO: Preparing lowrisc:prim:sparse_fsm:0
INFO: Preparing lowrisc:prim:subreg:0
INFO: Preparing lowrisc:prim:util:0.1
INFO: Preparing lowrisc:ip:lc_ctrl_state_pkg:0.1
INFO: Preparing lowrisc:prim:and2:0
INFO: Preparing lowrisc:prim:buf:0
INFO: Preparing lowrisc:prim:clock_mux2:0
INFO: Preparing lowrisc:prim:flop:0
INFO: Preparing lowrisc:prim:flop_en:0
INFO: Preparing lowrisc:prim:onehot_check:0
INFO: Preparing lowrisc:prim:pad_wrapper:0
INFO: Preparing lowrisc:prim:xnor2:0
INFO: Preparing lowrisc:prim:xor2:0
INFO: Preparing lowrisc:prim:blanker:0
INFO: Preparing lowrisc:prim:flop_2sync:0
INFO: Preparing lowrisc:prim:mubi:0.1
INFO: Preparing lowrisc:prim:reg_we_check:0
INFO: Preparing lowrisc:prim:diff_decode:0
INFO: Preparing lowrisc:prim:fifo:0
INFO: Preparing lowrisc:prim:rst_sync:0
INFO: Preparing lowrisc:tlul:headers:0.1
INFO: Preparing lowrisc:ip:lc_ctrl_pkg:0.1
INFO: Preparing lowrisc:prim:esc:0
INFO: Preparing lowrisc:tlul:trans_intg:0.1
INFO: Preparing lowrisc:ip:csrng_pkg:0.1
INFO: Preparing lowrisc:prim:alert:0
INFO: Preparing lowrisc:prim:lc_sync:0.1
INFO: Preparing lowrisc:tlul:common:0.1
INFO: Preparing lowrisc:ip:edn_pkg:0.1
INFO: Preparing lowrisc:prim:all:0.1
INFO: Preparing lowrisc:tlul:adapter_reg:0.1
INFO: Preparing lowrisc:tlul:adapter_sram:0.1
INFO: Preparing lowrisc:tlul:lc_gate:0.1
INFO: Preparing lowrisc:tlul:socket_1n:0.1
INFO: Preparing lowrisc:tlul:socket_m1:0.1
INFO: Preparing lowrisc:tlul:sram2tlul:0.1
INFO: Preparing lowrisc:ip:keymgr_pkg:0.1
INFO: Preparing lowrisc:ip:tlul:0.1
INFO: Preparing lowrisc:ip:aes:1.0
INFO: Generating lowrisc:prim:prim_pkg-impl:0.1
Creating prim_pkg.sv
Core file written to prim_pkg.core.
INFO: Generating lowrisc:prim:and2-impl:0
Implementations for primitive and2: generic, xilinx
Inspecting generic module /home/work/test/opentitan/hw/ip/prim_generic/rtl/prim_generic_and2.sv
Creating SystemVerilog module for abstract primitive
Abstract primitive written to /tmp/lowrisc_prim_and2-impl_0fevinth5/prim_and2.sv
Creating core file for primitive and2.
Core file written to /tmp/lowrisc_prim_and2-impl_0fevinth5/prim_and2.core
INFO: Generating lowrisc:prim:buf-impl:0
Implementations for primitive buf: xilinx, generic
Inspecting generic module /home/work/test/opentitan/hw/ip/prim_generic/rtl/prim_generic_buf.sv
Creating SystemVerilog module for abstract primitive
Abstract primitive written to /tmp/lowrisc_prim_buf-impl_04q0fts9f/prim_buf.sv
Creating core file for primitive buf.
Core file written to /tmp/lowrisc_prim_buf-impl_04q0fts9f/prim_buf.core
INFO: Generating lowrisc:prim:clock_mux2-impl:0
Implementations for primitive clock_mux2: xilinx, generic
Inspecting generic module /home/work/test/opentitan/hw/ip/prim_generic/rtl/prim_generic_clock_mux2.sv
Creating SystemVerilog module for abstract primitive
Abstract primitive written to /tmp/lowrisc_prim_clock_mux2-impl_0kcf6x958/prim_clock_mux2.sv
Creating core file for primitive clock_mux2.
Core file written to /tmp/lowrisc_prim_clock_mux2-impl_0kcf6x958/prim_clock_mux2.core
INFO: Generating lowrisc:prim:flop-impl:0
Implementations for primitive flop: generic, xilinx
Inspecting generic module /home/work/test/opentitan/hw/ip/prim_generic/rtl/prim_generic_flop.sv
'<' not supported between instances of 'BranchNode' and 'BranchNode'
Verible parser failed, using regex fallback instead.
Creating SystemVerilog module for abstract primitive
Abstract primitive written to /tmp/lowrisc_prim_flop-impl_0mcw1e5nr/prim_flop.sv
Creating core file for primitive flop.
Core file written to /tmp/lowrisc_prim_flop-impl_0mcw1e5nr/prim_flop.core
INFO: Generating lowrisc:prim:flop_en-impl:0
Implementations for primitive flop_en: generic, xilinx
Inspecting generic module /home/work/test/opentitan/hw/ip/prim_generic/rtl/prim_generic_flop_en.sv
'<' not supported between instances of 'BranchNode' and 'BranchNode'
Verible parser failed, using regex fallback instead.
Creating SystemVerilog module for abstract primitive
Abstract primitive written to /tmp/lowrisc_prim_flop_en-impl_0olikxx8l/prim_flop_en.sv
Creating core file for primitive flop_en.
Core file written to /tmp/lowrisc_prim_flop_en-impl_0olikxx8l/prim_flop_en.core
INFO: Generating lowrisc:prim:pad_wrapper-impl:0
Implementations for primitive pad_wrapper: xilinx, generic
Inspecting generic module /home/work/test/opentitan/hw/ip/prim_generic/rtl/prim_generic_pad_wrapper.sv
'<' not supported between instances of 'BranchNode' and 'BranchNode'
Verible parser failed, using regex fallback instead.
Creating SystemVerilog module for abstract primitive
Abstract primitive written to /tmp/lowrisc_prim_pad_wrapper-impl_0t7rjld_4/prim_pad_wrapper.sv
Creating core file for primitive pad_wrapper.
Core file written to /tmp/lowrisc_prim_pad_wrapper-impl_0t7rjld_4/prim_pad_wrapper.core
INFO: Generating lowrisc:prim:xnor2-impl:0
Implementations for primitive xnor2: generic
Inspecting generic module /home/work/test/opentitan/hw/ip/prim_generic/rtl/prim_generic_xnor2.sv
Creating SystemVerilog module for abstract primitive
Abstract primitive written to /tmp/lowrisc_prim_xnor2-impl_0d74zjilu/prim_xnor2.sv
Creating core file for primitive xnor2.
Core file written to /tmp/lowrisc_prim_xnor2-impl_0d74zjilu/prim_xnor2.core
INFO: Generating lowrisc:prim:xor2-impl:0
Implementations for primitive xor2: xilinx, generic
Inspecting generic module /home/work/test/opentitan/hw/ip/prim_generic/rtl/prim_generic_xor2.sv
Creating SystemVerilog module for abstract primitive
Abstract primitive written to /tmp/lowrisc_prim_xor2-impl_0mcjc011y/prim_xor2.sv
Creating core file for primitive xor2.
Core file written to /tmp/lowrisc_prim_xor2-impl_0mcjc011y/prim_xor2.core
INFO: Wrote dependency graph to /home/work/test/opentitan/scratch/master/aes-syn-dc/default/syn-icarus/lowrisc_ip_aes_1.0.deps-after-generators.dot
INFO: Setting up project

[make]: pre_build
mkdir -p /home/work/test/opentitan/scratch/master/aes-syn-dc/default
[make]: do_build
cd /home/work/test/opentitan/scratch/master/aes-syn-dc/default/syn-icarus && dc_shell-xg-t -f /home/work/test/opentitan/hw/syn/tools/dc/run-syn.tcl 2>&1 | tee /home/work/test/opentitan/scratch/master/aes-syn-dc/default/synthesis.log

Initializing...
Initializing gui preferences from file  /home/.synopsys_dv_prefs.tcl
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
#
# Simple tcl script for DC to do some wire-load-model-based test syntheses.
#####################
##  PREPARE FLOW   ##
#####################
proc get_env_var {name} {
  if {[info exists ::env($name)]} {
    set val "[set ::env([set name])]"
    puts "::env($name) = $val"
    return $val
  } else {
    puts "ERROR: Script run without $name environment variable."
    quit
  }
}
set FOUNDRY_ROOT       [get_env_var "FOUNDRY_ROOT"]
::env(FOUNDRY_ROOT) = 
set SYN_ROOT           [get_env_var "SYN_ROOT"]
::env(SYN_ROOT) = /home/work/test/opentitan/hw/syn
/home/work/test/opentitan/hw/syn
set SV_FLIST           [get_env_var "SV_FLIST"]
::env(SV_FLIST) = /home/work/test/opentitan/scratch/master/aes-syn-dc/default/syn-icarus/lowrisc_ip_aes_1.0.scr
/home/work/test/opentitan/scratch/master/aes-syn-dc/default/syn-icarus/lowrisc_ip_aes_1.0.scr
set BUILD_DIR          [get_env_var "BUILD_DIR"]
::env(BUILD_DIR) = /home/work/test/opentitan/scratch/master/aes-syn-dc/default
/home/work/test/opentitan/scratch/master/aes-syn-dc/default
set DUT                [get_env_var "DUT"]
::env(DUT) = aes
aes
set CONSTRAINT         [get_env_var "CONSTRAINT"]
::env(CONSTRAINT) = /home/work/test/opentitan/hw/syn/tools/dc/gtech-constraints.sdc
/home/work/test/opentitan/hw/syn/tools/dc/gtech-constraints.sdc
set FOUNDRY_CONSTRAINT [get_env_var "FOUNDRY_CONSTRAINT"]
::env(FOUNDRY_CONSTRAINT) = 
set PARAMS             [get_env_var "PARAMS"]
::env(PARAMS) = 
set POST_ELAB_SCRIPT   [get_env_var "POST_ELAB_SCRIPT"]
::env(POST_ELAB_SCRIPT) = /home/work/test/opentitan/hw/ip/aes/syn/aes_post_elab_gtech.tcl
/home/work/test/opentitan/hw/ip/aes/syn/aes_post_elab_gtech.tcl
set TERMINATION_STAGE  [get_env_var "TERMINATION_STAGE"]
::env(TERMINATION_STAGE) = compile
compile
# This is not a CDC run.
set IS_CDC_RUN 0
0
# if in interactive mode, do not exit at the end of the script
if { [info exists ::env(RUN_INTERACTIVE)] } {
  set RUN_INTERACTIVE 1
} else {
  set RUN_INTERACTIVE 0
}
0
# paths
set WORKLIB  "${BUILD_DIR}/WORK"
/home/work/test/opentitan/scratch/master/aes-syn-dc/default/WORK
set REPDIR   "${BUILD_DIR}/REPORTS"
/home/work/test/opentitan/scratch/master/aes-syn-dc/default/REPORTS
set DDCDIR   "${BUILD_DIR}/DDC"
/home/work/test/opentitan/scratch/master/aes-syn-dc/default/DDC
set RESULTDIR "${BUILD_DIR}/results"
/home/work/test/opentitan/scratch/master/aes-syn-dc/default/results
set VLOGDIR  "${BUILD_DIR}/NETLISTS"
/home/work/test/opentitan/scratch/master/aes-syn-dc/default/NETLISTS
exec mkdir -p ${REPDIR} ${DDCDIR} ${VLOGDIR} ${WORKLIB} ${RESULTDIR}
# define work lib path
define_design_lib WORK -path $WORKLIB
1
########################
## Library Setup      ##
########################
if {$FOUNDRY_ROOT != ""} {
  # ASIC lib setup for DC.
  source "${FOUNDRY_ROOT}/syn/dc/setup.tcl"
  # this PRIM_DEFAULT_IMPL selects the appropriate technology by defining
  # PRIM_DEFAULT_IMPL=prim_pkg::Impl<tech identifier>
  # PRIM_DEFAULT_IMPL is set inside the library setup script
  set DEFINE "PRIM_DEFAULT_IMPL=${PRIM_DEFAULT_IMPL}+${PRIM_STD_CELL_VARIANT}"
} else {
  # GTECH lib setup for DC.
  source "${SYN_ROOT}/tools/dc/gtech-setup.tcl"
  # This black-boxes the 1p and 2p memory models (used for GTECH runs only).
  set DEFINE "SYNTHESIS_MEMORY_BLACK_BOXING=TRUE"
}
SYNTHESIS_MEMORY_BLACK_BOXING=TRUE
#######################
## CONFIGURATIONS   ###
#######################
# Define the verification setup file for Formality
set_svf ${RESULTDIR}/${DUT}.svf
1
# Setup SAIF Name Mapping Database
saif_map -start
Information: The SAIF name mapping information database is now active. (PWR-602)
1
###The following variable helps verification when there are differences between DC and FM while inferring logical hierarchies
set_app_var hdlin_enable_hier_map true
true
###########################
##   Env var file        ##
###########################
set fp [open "${BUILD_DIR}/env_variables.tcl" w+]
file11
puts $fp "set ::env(RUN_INTERACTIVE) 1"
puts $fp "set ::env(SYN_ROOT) $SYN_ROOT"
puts $fp "set ::env(FOUNDRY_ROOT) $FOUNDRY_ROOT"
puts $fp "set ::env(PARAMS) $PARAMS"
puts $fp "set ::env(SV_FLIST) $SV_FLIST"
puts $fp "set ::env(BUILD_DIR) $BUILD_DIR"
puts $fp "set ::env(DUT) $DUT"
puts $fp "set ::env(CONSTRAINT) $CONSTRAINT"
puts $fp "set ::env(FOUNDRY_CONSTRAINT) $FOUNDRY_CONSTRAINT"
puts $fp "set ::env(POST_ELAB_SCRIPT) $POST_ELAB_SCRIPT"
close $fp
###########################
##   ELABORATE DESIGN    ##
###########################
puts ${SV_FLIST}
/home/work/test/opentitan/scratch/master/aes-syn-dc/default/syn-icarus/lowrisc_ip_aes_1.0.scr
# delete previous designs.
remove_design -designs
1
sh rm -rf $WORKLIB/*
puts "${DEFINE}"
SYNTHESIS_MEMORY_BLACK_BOXING=TRUE
puts ${SV_FLIST}
/home/work/test/opentitan/scratch/master/aes-syn-dc/default/syn-icarus/lowrisc_ip_aes_1.0.scr
analyze -vcs "-sverilog +define+${DEFINE} -f ${SV_FLIST}" > "${REPDIR}/analyze.rpt"
if { $TERMINATION_STAGE == "analyze" } { exit }
elaborate  ${DUT} -parameters ${PARAMS}                   > "${REPDIR}/elab.rpt"
current_design ${DUT}
Error: Can't find design 'aes'. (UID-109)
Error: Current design is not defined. (UID-4)
link                                                      > "${REPDIR}/link.rpt"
check_design                                              > "${REPDIR}/check.rpt"
set_verification_top
Error: Current design is not defined. (UID-4)
0
if {$POST_ELAB_SCRIPT != ""} {
  source ${POST_ELAB_SCRIPT}
}
write_file -format ddc -hierarchy -output "${DDCDIR}/elab.ddc"
Error: No files or designs were specified. (UID-22)
1
if { $TERMINATION_STAGE == "elab" } { exit }
#############################
##   CLOCK GATING SETUP    ##
#############################
# be more specific if defaults do not suffice
# set_clock_gating_style -num_stages 1                   #                        -positive_edge_logic integrated #                        -control_point before           #                        -control_signal scan_enable
###########################
##   APPLY CONSTRAINTS   ##
###########################
if {$CONSTRAINT != ""} {
  puts "Applying constraints for ${DUT}"
  source "${CONSTRAINT}"
  puts "Done applying constraints for ${DUT}"
}
Applying constraints for aes
Error: Current design is not defined. (UID-4)
Error: Can't find design 'prim_generic_xor*'. (UID-109)
Error: Value for list 'object_list' must have 1 elements. (CMD-036)
Error: Current design is not defined. (UID-4)
Error: Can't find design 'prim_generic_buf*'. (UID-109)
Error: Value for list 'object_list' must have 1 elements. (CMD-036)
Error: Current design is not defined. (UID-4)
Error: Can't find design 'prim_generic_clock_buf*'. (UID-109)
Error: Value for list 'object_list' must have 1 elements. (CMD-036)
Error: Current design is not defined. (UID-4)
Error: Can't find design 'prim_generic_inv*'. (UID-109)
Error: Value for list 'object_list' must have 1 elements. (CMD-036)
Error: Current design is not defined. (UID-4)
Error: Can't find design 'prim_generic_clock_inv*'. (UID-109)
Error: Value for list 'object_list' must have 1 elements. (CMD-036)
Error: Current design is not defined. (UID-4)
Error: Can't find design 'prim_generic_clock_mux*'. (UID-109)
Error: Value for list 'object_list' must have 1 elements. (CMD-036)
Error: Current design is not defined. (UID-4)
Error: Can't find design 'prim_generic_flop*'. (UID-109)
Error: Value for list 'object_list' must have 1 elements. (CMD-036)
Done applying constraints for aes
if {$FOUNDRY_CONSTRAINT != ""} {
  puts "Applying foundry constraints for ${DUT}"
  source "${FOUNDRY_CONSTRAINT}"
  puts "Done applying foundry constraints for ${DUT}"
}
# If hold time should be fixed
# set_fix_hold ${CLK_PIN}
######################
##    MAP DESIGN    ##
######################
# only use compile_ultra if the foundry library is defined.
# otherwise we can only do a compile with gtech cells.
if {$FOUNDRY_ROOT == ""} {
  # enable auto ungrouping and boundary optimization for
  # gtech experiments, in order to approximate actual
  # implementation runs with compile_ultra.
  compile -gate_clock                       -scan                             -boundary_optimization            -auto_ungroup area      > "${REPDIR}/compile.rpt"
} else {
  # preserve hierarchy for reports
  compile_ultra -gate_clock                 -scan                       -no_autoungroup > "${REPDIR}/compile.rpt"
}
#################
##   NETLIST   ##
#################
change_names -rules verilog -hierarchy
Error: Current design is not defined. (UID-4)
0
define_name_rules fixbackslashes -allowed "A-Za-z0-9_" -first_restricted "\\" -remove_chars
1
change_names -rule fixbackslashes -h
Error: Current design is not defined. (UID-4)
0
# Change the name in case the netlist has not been mapped against a real ASIC lib.
if {$FOUNDRY_ROOT == ""} {
  set NETLIST_NAME "mapped_gtech"
} else {
  set NETLIST_NAME "mapped"
}
mapped_gtech
write_file -format ddc     -hierarchy -output "${DDCDIR}/${NETLIST_NAME}.ddc"
Error: No files or designs were specified. (UID-22)
0
write_file -format verilog -hierarchy -output "${VLOGDIR}/${NETLIST_NAME}.v"
Error: No files or designs were specified. (UID-22)
0
# Write final SDC
write_sdc -nosplit ${RESULTDIR}/${DUT}.final.sdc
Error: Current design is not defined. (UID-4)
0
# If SAIF is used, write out SAIF name mapping file for PrimeTime-PX
saif_map -type ptpx -write_map ${RESULTDIR}/${DUT}.${NETLIST_NAME}.SAIF.namemap
Error: Current design is not defined. (UID-4)
0
if { $TERMINATION_STAGE == "compile" } { exit }

Memory usage for main task 61 Mbytes.
Memory usage for this session 61 Mbytes.
CPU usage for this session 0 seconds ( 0.00 hours ).

Thank you...
[make]: post_build
[make]: build_result
/home/work/test/opentitan/hw/syn/tools/dc/parse-syn-report.py --dut aes --expand-modules aes --expand-depth 1 --log-path /home/work/test/opentitan/scratch/master/aes-syn-dc/default --rep-path /home/work/test/opentitan/scratch/master/aes-syn-dc/default/REPORTS --out-dir /home/work/test/opentitan/scratch/master/aes-syn-dc/default --termination-stage compile
------------- Summary -------------
Flow Warnings:      0
Flow Errors:        31
Analyze Warnings:   68
Analyze Errors:     1
Elab Warnings:      0
Elab Errors:        1
Compile Warnings:   0
Compile Errors:     1
-----------------------------------
Synthesis not successful.
make: *** [/home/work/test/opentitan/hw/syn/tools/dvsim/syn.mk:38: build_result] Error 1

And the analyze.rpt show below:

Running PRESTO HDLC
Warning:  :0: Redefining macro 'SYNTHESIS' with value '1' to ''. (VER-540)
Compiling source file ../src/lowrisc_constants_top_pkg_0/rtl/top_pkg.sv
Compiling source file ../src/lowrisc_dv_pins_if_0/pins_if.sv
Compiling source file ../src/lowrisc_ip_entropy_src_pkg_0.1/rtl/entropy_src_pkg.sv
Warning:  ../src/lowrisc_ip_entropy_src_pkg_0.1/rtl/entropy_src_pkg.sv:12: Parameter keyword used in local parameter declaration. (VER-329)
Compiling source file ../src/lowrisc_prim_abstract_prim_pkg_0.1/prim_pkg.sv
Compiling source file ../src/lowrisc_prim_cipher_pkg_0.1/rtl/prim_cipher_pkg.sv
Warning:  ../src/lowrisc_prim_cipher_pkg_0.1/rtl/prim_cipher_pkg.sv:23: Parameter keyword used in local parameter declaration. (VER-329)
Compiling source file ../src/lowrisc_prim_generic_and2_0/rtl/prim_generic_and2.sv
Opening include file ../src/lowrisc_prim_assert_0.1/rtl/prim_assert.sv
Opening include file ../src/lowrisc_prim_assert_0.1/rtl/prim_assert_standard_macros.svh
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_assert_standard_macros.svh:51: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_assert_standard_macros.svh:63: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_assert_standard_macros.svh:67: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_assert_standard_macros.svh:67: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_assert_standard_macros.svh:73: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_assert_standard_macros.svh:73: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_assert_standard_macros.svh:79: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_assert_standard_macros.svh:79: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_assert_standard_macros.svh:82: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_assert_standard_macros.svh:82: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_assert_standard_macros.svh:85: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_assert_standard_macros.svh:85: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_assert.sv:119: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_assert.sv:119: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_assert.sv:124: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_assert.sv:124: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_assert.sv:129: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_assert.sv:129: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_assert.sv:142: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_assert.sv:142: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_assert.sv:156: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_assert.sv:156: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_assert.sv:167: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_assert.sv:167: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Opening include file ../src/lowrisc_prim_assert_0.1/rtl/prim_assert_sec_cm.svh
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_assert_sec_cm.svh:32: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_assert_sec_cm.svh:32: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_assert_sec_cm.svh:35: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_assert_sec_cm.svh:35: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_assert_sec_cm.svh:38: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_assert_sec_cm.svh:38: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_assert_sec_cm.svh:41: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_assert_sec_cm.svh:41: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_assert_sec_cm.svh:44: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_assert_sec_cm.svh:44: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_assert_sec_cm.svh:49: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_assert_sec_cm.svh:49: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_assert_sec_cm.svh:49: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_assert_sec_cm.svh:49: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_assert_sec_cm.svh:52: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_assert_sec_cm.svh:52: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_assert_sec_cm.svh:52: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_assert_sec_cm.svh:52: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_assert_sec_cm.svh:55: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_assert_sec_cm.svh:55: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_assert_sec_cm.svh:55: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_assert_sec_cm.svh:55: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_assert_sec_cm.svh:58: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_assert_sec_cm.svh:58: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_assert_sec_cm.svh:58: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_assert_sec_cm.svh:58: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_assert_sec_cm.svh:61: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_assert_sec_cm.svh:61: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_assert_sec_cm.svh:61: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_assert_sec_cm.svh:61: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Opening include file ../src/lowrisc_prim_assert_0.1/rtl/prim_flop_macros.sv
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_flop_macros.sv:24: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_flop_macros.sv:24: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_flop_macros.sv:24: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_flop_macros.sv:44: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_flop_macros.sv:44: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_flop_macros.sv:44: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Warning:  ../src/lowrisc_prim_assert_0.1/rtl/prim_flop_macros.sv:44: The 'macro default arguments' construct is not supported.  It will be ignored. (VER-104)
Compiling source file ../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv
Opening include file ../src/lowrisc_prim_assert_0.1/rtl/prim_assert.sv
Compiling source file ../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv
Opening include file ../src/lowrisc_prim_assert_0.1/rtl/prim_assert.sv
Compiling source file ../src/lowrisc_prim_generic_xnor2_0/rtl/prim_generic_xnor2.sv
Opening include file ../src/lowrisc_prim_assert_0.1/rtl/prim_assert.sv
Compiling source file ../src/lowrisc_prim_generic_xor2_0/rtl/prim_generic_xor2.sv
Opening include file ../src/lowrisc_prim_assert_0.1/rtl/prim_assert.sv
Compiling source file ../src/lowrisc_prim_pad_wrapper_pkg_0/rtl/prim_pad_wrapper_pkg.sv
Warning:  ../src/lowrisc_prim_pad_wrapper_pkg_0/rtl/prim_pad_wrapper_pkg.sv:24: Parameter keyword used in local parameter declaration. (VER-329)
Compiling source file ../src/lowrisc_prim_secded_0.1/rtl/prim_secded_pkg.sv
Warning:  ../src/lowrisc_prim_secded_0.1/rtl/prim_secded_pkg.sv:81: Parameter keyword used in local parameter declaration. (VER-329)
Compiling source file ../src/lowrisc_prim_secded_0.1/rtl/prim_secded_22_16_dec.sv
Compiling source file ../src/lowrisc_prim_secded_0.1/rtl/prim_secded_22_16_enc.sv
Compiling source file ../src/lowrisc_prim_secded_0.1/rtl/prim_secded_28_22_dec.sv
Compiling source file ../src/lowrisc_prim_secded_0.1/rtl/prim_secded_28_22_enc.sv
Compiling source file ../src/lowrisc_prim_secded_0.1/rtl/prim_secded_39_32_dec.sv
Compiling source file ../src/lowrisc_prim_secded_0.1/rtl/prim_secded_39_32_enc.sv
Compiling source file ../src/lowrisc_prim_secded_0.1/rtl/prim_secded_64_57_dec.sv
Compiling source file ../src/lowrisc_prim_secded_0.1/rtl/prim_secded_64_57_enc.sv
Compiling source file ../src/lowrisc_prim_secded_0.1/rtl/prim_secded_72_64_dec.sv
Compiling source file ../src/lowrisc_prim_secded_0.1/rtl/prim_secded_72_64_enc.sv
Compiling source file ../src/lowrisc_prim_secded_0.1/rtl/prim_secded_hamming_22_16_dec.sv
Compiling source file ../src/lowrisc_prim_secded_0.1/rtl/prim_secded_hamming_22_16_enc.sv
Compiling source file ../src/lowrisc_prim_secded_0.1/rtl/prim_secded_hamming_39_32_dec.sv
Compiling source file ../src/lowrisc_prim_secded_0.1/rtl/prim_secded_hamming_39_32_enc.sv
Compiling source file ../src/lowrisc_prim_secded_0.1/rtl/prim_secded_hamming_72_64_dec.sv
Compiling source file ../src/lowrisc_prim_secded_0.1/rtl/prim_secded_hamming_72_64_enc.sv
Compiling source file ../src/lowrisc_prim_secded_0.1/rtl/prim_secded_hamming_76_68_dec.sv
Compiling source file ../src/lowrisc_prim_secded_0.1/rtl/prim_secded_hamming_76_68_enc.sv
Compiling source file ../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_22_16_dec.sv
Compiling source file ../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_22_16_enc.sv
Compiling source file ../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_28_22_dec.sv
Compiling source file ../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_28_22_enc.sv
Compiling source file ../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_dec.sv
Compiling source file ../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv
Compiling source file ../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_64_57_dec.sv
Compiling source file ../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_64_57_enc.sv
Compiling source file ../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_72_64_dec.sv
Compiling source file ../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_72_64_enc.sv
Compiling source file ../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_hamming_22_16_dec.sv
Compiling source file ../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_hamming_22_16_enc.sv
Compiling source file ../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_hamming_39_32_dec.sv
Compiling source file ../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_hamming_39_32_enc.sv
Compiling source file ../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_hamming_72_64_dec.sv
Compiling source file ../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_hamming_72_64_enc.sv
Compiling source file ../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_hamming_76_68_dec.sv
Compiling source file ../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_hamming_76_68_enc.sv
Compiling source file ../src/lowrisc_prim_xilinx_and2_0/rtl/prim_xilinx_and2.sv
Opening include file ../src/lowrisc_prim_assert_0.1/rtl/prim_assert.sv
Compiling source file ../src/lowrisc_prim_xilinx_buf_0/rtl/prim_xilinx_buf.sv
Compiling source file ../src/lowrisc_prim_xilinx_clock_mux2_0/rtl/prim_xilinx_clock_mux2.sv
Opening include file ../src/lowrisc_prim_assert_0.1/rtl/prim_assert.sv
Warning:  ../src/lowrisc_prim_xilinx_clock_mux2_0/rtl/prim_xilinx_clock_mux2.sv:33: The construct 'assert property' is not supported in synthesis; it is ignored. (VER-708)
Warning:  ../src/lowrisc_prim_xilinx_clock_mux2_0/rtl/prim_xilinx_clock_mux2.sv:34: The construct 'assert property' is not supported in synthesis; it is ignored. (VER-708)
Compiling source file ../src/lowrisc_prim_xilinx_flop_0/rtl/prim_xilinx_flop.sv
Opening include file ../src/lowrisc_prim_assert_0.1/rtl/prim_assert.sv
Compiling source file ../src/lowrisc_prim_xilinx_flop_en_0/rtl/prim_xilinx_flop_en.sv
Opening include file ../src/lowrisc_prim_assert_0.1/rtl/prim_assert.sv
Compiling source file ../src/lowrisc_prim_xilinx_xor2_0/rtl/prim_xilinx_xor2.sv
Opening include file ../src/lowrisc_prim_assert_0.1/rtl/prim_assert.sv
Compiling source file ../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv
Opening include file ../src/lowrisc_prim_assert_0.1/rtl/prim_assert.sv
Error:  ../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv:141: The number of parameters for the 'ASSERT_KNOWN' macro doesn't match its definition. (VER-927)
*** Presto compilation terminated with 1 errors. ***
Loading db file '/tools/edaTools/synopsys/syn/O-2018.06-SP1/libraries/syn/gtech.db'
Loading db file '/tools/edaTools/synopsys/syn/O-2018.06-SP1/libraries/syn/dw_foundation.sldb'
rswarbrick commented 11 months ago

I think this is a tooling problem. As far as I can tell, the ASSERT_KNOWN macro is defined correctly, with two required arguments and two optional ones that can come after.

I'm afraid I don't know the "Presto HDLC" tool: is it something that OpenTitan explicitly supports?

gzyangcs commented 11 months ago

@rswarbrick yes, i blieve the macro is fine too. The "Presto HDLC" is running by DC to compile source file. I had suspend error is come from DC. So i running DC by script and it shows everything is fine. So, do i need to reinstall DC?

rswarbrick commented 11 months ago

If I understand you correctly, that's an IT question about how you install your synthesis tool. I'm afraid this probably isn't the right place to ask :-)

cdgori commented 11 months ago

@msfschaffner - do you know the minimum version of DC required to synthesize? This is using O-2018.06-SP1 which is quite old.

@vogelpi - do you know if anyone has tried synth on just the AES using the DC flow? I am wondering if the icarus flist (/home/work/test/opentitan/scratch/master/aes-syn-dc/default/syn-icarus/lowrisc_ip_aes_1.0.scr) will work correctly when using DC, as I would expect these asserts to be ifdef'd/compiled out for synthesis/elab.

vogelpi commented 11 months ago

@cdgori , I am aware that @ballifatih has been experimenting with the AES S-Box and DC quite recently but I don't know whether he used the in-tree synthesis flow or something custom. I am aware that also someone else from the community tried to synthesize AES with DC recently and faced some issues. But there, I don't have any visibility into the used tool version or flow.

I would also expect these asserts to get removed for synthesis/elab. This is a very good point Chris. In this particular case here, synthesis fails in prim_arbiter_fixed.sv but AES doesn't use this primitive, nor does any of the dependencies. At least we don't compile the file in the Yosys setup which is able to generate a functionally correct netlist (see hw/ip/aes/pre_syn/syn_yosys.sh).

ballifatih commented 11 months ago

I used the other synthesis script for AES S-box: ./util/dvsim/dvsim.py hw/ip/aes/syn/aes_syn_cfg.hjson. I also get some errors now when I try with the other aes_gtech_syn_cfg.hjson script. I do not know what is the difference between the two synthesis scripts though.

Since I was able to get a netlist consisting of library cells with aes_syn_cfg.hjson, that was enough for me back then.