[chip-test,sival] chip_sw_usbdev_aon_wake_resume

alees24 commented 11 months ago

chip_sw_usbdev_aon_wake_resume

Rust

Unknown

Yes

alees24

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

[x] Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
[x] Device-side (C) component developed
[x] Bazel build rules developed
[x] Host-side component developed
[x] HJSON test plan updated with test name (so it shows up in the dashboard)
[x] Test added to dvsim nightly regression (and passing at time of checking)
[x] For SiVal test cases, test is running relevant FPGA or silicon regression

estimate 2

pamaury commented 6 months ago

Clarify whether this test can actually be implemented, also it's not listed in the testplan.

alees24 commented 2 months ago

estimate 0

lowRISC / opentitan