[chip-test,sival] chip_sw_usbdev_aon_wake_disconnect

[alees24]

Test point name

chip_sw_usbdev_aon_wake_disconnect

Host side component

Rust

OpenTitanTool infrastructure implemented

Unknown

Silicon Validation (SiVal)

Yes

Emulation Targets

• [ ] None
• [X] CW310
• [X] Hyperdebug + CW310

Contact person

alees24

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

• [x] Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
• [x] Device-side (C) component developed
• [x] Bazel build rules developed
• [x] Host-side component developed
• [x] HJSON test plan updated with test name (so it shows up in the dashboard)
• [x] Test added to dvsim nightly regression (and passing at time of checking)
• [x] For SiVal test cases, test is running relevant FPGA or silicon regression

estimate 3

[alees24]

estimate 0