[chip-test, sival] AES idle test

[vrozic]

Test point name

chip_sw_aes_idle

Host side component

None

OpenTitanTool infrastructure implemented

None

Silicon Validation (SiVal)

Yes

Emulation Targets

• [ ] None
• [X] CW310
• [ ] Hyperdebug + CW310

Contact person

vogelpi

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

• [ ] Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
• [ ] Device-side (C) component developed
• [ ] Bazel build rules developed
• [ ] Host-side component developed
• [ ] HJSON test plan updated with test name (so it shows up in the dashboard)
• [ ] Test added to dvsim nightly regression (and passing at time of checking)
• [ ] For SiVal test cases, test is running relevant FPGA or silicon regression

estimate: 2

[vrozic]

Based on PR: #19783