[chip-test] chip_sw_uart_tx_rx_alt_clk_freq - Githubissues

lowRISC / opentitan

OpenTitan: Open source silicon root of trust

https://www.opentitan.org

Apache License 2.0

2.58k stars 775 forks source link

[chip-test] chip_sw_uart_tx_rx_alt_clk_freq #19999

Open rswarbrick opened 1 year ago

rswarbrick commented 1 year ago

Test point name

chip_sw_uart_tx_rx_alt_clk_freq

Host side component

Unknown

OpenTitanTool infrastructure implemented

None

Silicon Validation (SiVal)

Yes

Emulation Targets

[ ] None
[ ] CW310
[x] Hyperdebug + CW310

Contact person

@rswarbrick

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

[ ] Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
[ ] Device-side (C) component developed
[ ] Bazel build rules developed
[ ] Host-side component developed
[ ] Test added to dvsim nightly regression (and passing at time of checking)
[ ] For SiVal test cases, test is running relevant FPGA or silicon regression

estimate 4

rswarbrick commented 1 year ago

I'm not completely convinced that this testpoint makes much sense in a sival context, because I think it needs RMA parts, which won't be generally available. I'm making this issue to keep things in track with the testplan in chip_uart_testplan.hjson, but I wouldn't be surprised if we end up closing this with no test.