[chip-test, sival] chip_sw_rv_core_ibex_icache_scrambled_access

GregAC commented 11 months ago

None

None

Yes

@GregAC

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

[ ] Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
[ ] Device-side (C) component developed
[ ] Bazel build rules developed
[ ] Host-side component developed
[ ] HJSON test plan updated with test name (so it shows up in the dashboard)
[ ] Test added to dvsim nightly regression (and passing at time of checking)
[ ] For SiVal test cases, test is running relevant FPGA or silicon regression

estimate 0.5

HU90m commented 10 months ago

HU90m commented 8 months ago

lowRISC / opentitan