[chip-test, sival] chip_sw_rv_core_ibex_smoke

[GregAC]

Test point name

chip_sw_rv_core_ibex_smoke

Host side component

None

OpenTitanTool infrastructure implemented

None

Silicon Validation (SiVal)

Yes

Emulation Targets

• [ ] None
• [X] CW310
• [ ] Hyperdebug + CW310

Contact person

@GregAC

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

• [ ] Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
• [ ] Device-side (C) component developed
• [ ] Bazel build rules developed
• [ ] Host-side component developed
• [ ] HJSON test plan updated with test name (so it shows up in the dashboard)
• [ ] Test added to dvsim nightly regression (and passing at time of checking)
• [ ] For SiVal test cases, test is running relevant FPGA or silicon regression

estimate 4

[GregAC]

Note we can at least partially auto-generate this with RISCV DV. Perhaps use that to generate a few fragments that are then stitched together with hand-written code. We can use the Ibex testbench coverage setup to ensure the test does execute every instruction.

A key property will be to ensure that if an instruction doesn't execute correctly that some aspect of the register state that we check will be affected. It may make sense to do multiple register state checks at different points rather than just one at the end to make this property easier to obtain.

[HU90m]

@GregAC

1. For the CSR instructions, is one instance of each of CSR{W,S,C} fine?
2. Can you think of a nice way of executing and checking ecall, ebreak, mret and dret?

[GregAC]

For the CSR instructions, is one instance of each of CSR{W,S,C} fine?

Yes, this test isn't aiming to verify CSR details just the instructions themselves

Can you think of a nice way of executing and checking ecall, ebreak, mret and dret?

Perhaps we just skip dret as that is fiddly or even impossible with the setup we have in silicon (you could maybe remap the debug ROM area to SRAM with the address remapper so you can write code that gets executed in debug mode but I think more effort than it's worth here). For the others you'll just to have an exception handler, ebreak will cause an exception by default as does ecall and you'll need an mret in that handler.

[jwnrt]

Closed by https://github.com/lowRISC/opentitan/pull/20372