[chip-test, sival] chip_sw_rv_core_ibex_mem_smoke

[GregAC]

Test point name

chip_sw_rv_core_ibex_mem_smoke

Host side component

None

OpenTitanTool infrastructure implemented

None

Silicon Validation (SiVal)

Yes

Emulation Targets

• [ ] None
• [X] CW310
• [ ] Hyperdebug + CW310

Contact person

@GregAC

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

• [ ] Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
• [ ] Device-side (C) component developed
• [ ] Bazel build rules developed
• [ ] Host-side component developed
• [ ] HJSON test plan updated with test name (so it shows up in the dashboard)
• [ ] Test added to dvsim nightly regression (and passing at time of checking)
• [ ] For SiVal test cases, test is running relevant FPGA or silicon regression

estimate 2

[jwnrt]

Closed by https://github.com/lowRISC/opentitan/pull/20504

[engdoreis]

Reopening this Issues because the test fails with SiVal target:

//sw/device/tests:rv_core_ibex_mem_test_functest_fpga_cw310_rom_with_fake_keys PASSED in 23.5s
//sw/device/tests:rv_core_ibex_mem_test_functest_fpga_cw310_sival_rom_ext PASSED in 24.0s
//sw/device/tests:rv_core_ibex_mem_test_functest_fpga_cw310_test_rom     PASSED in 23.9s
//sw/device/tests:rv_core_ibex_mem_test_functest_fpga_cw310_sival        FAILED in 19.4s