[chip-test] chip_sw_entropy_src_bypass_mode_health_tests

[vogelpi]

Test point name

https://github.com/lowRISC/opentitan/blob/master/hw/top_earlgrey/data/ip/chip_entropy_src_testplan.hjson#L95

Host side component

None

OpenTitanTool infrastructure implemented

None

Silicon Validation (SiVal)

Yes

Emulation Targets

• [ ] None
• [X] CW310
• [X] Hyperdebug + CW310

Contact person

@vogelpi @andreaskurth

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

• [ ] Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
• [ ] Device-side (C) component developed
• [ ] Bazel build rules developed
• [ ] Host-side component developed
• [ ] HJSON test plan updated with test name (so it shows up in the dashboard)
• [ ] Test added to dvsim nightly regression (and passing at time of checking)
• [ ] For SiVal test cases, test is running relevant FPGA or silicon regression

estimate 1

[johngt]

Needs the Bazel test point merged in the testplan. @vogelpi / @h-filali

[h-filali]

@johngt I couldn't find this test so I asked @vogelpi and we concluded that this test doesn't exist yet. Could you reopen this issue?

[johngt]

@h-filali - thanks. There might be some tests that I flag for adding to Bazel that don't have the FPGA/DVSIM test. This issue is already open so need to re-open it and I'll add it to the ones that are being tracked. Thanks!