Closed msfschaffner closed 2 months ago
We discussed this and determined that it would be good to also do a 1.8V IO signoff in addition to 3.3V. Need to assess how to adapt the constraints accordingly, especially for high speed IO on VIOA/VIOB (SPI_HOST, SPI_DEVICE).
@OTshimeon @meisnere @a-will @andreaskurth @vogelpi @jonmichelson @moidx
Moving into the PROD.M4 milestone, since timing signoff is not part of M2.
@OTshimeon as discussed with @moidx it would be great to have a one-pager on the timing part of the data sheet
@moidx Work is ongoing, at the moment on the closed source side. From an open source side we are done for the moment. Can you confirm @a-will ?
From the open-source side (not related to additional I/O voltage corners), we'll probably want to absorb some of the fixes back into the SDC file. Because I didn't have the tools to run a synthesis flow myself, I wasn't able to clear even syntax errors (nor any targeting errors for pins/cells/nets).
The open-source side has nothing to do for multiple voltage corners, I think. In that sense, this issue is probably miscategorized.
We are no longer expecting RTL changes as a result of remaining work here. Moving remaining efforts to M5.
We've discussed this in yesterday's sync up meeting and @OTshimeon confirmed that it's also Nuvoton's understanding that no further RTL changes are needed for this on the open source side. Shall we close the issue @moidx ?
@moidx @jesultra @jettr We just discussed this in the triage meeting and think it's complete per Nuvoton's feedback cited above. If we don't hear back from you until end of next week, we'll close this.
I don't quite understand what the ask or signoff this issue is requesting. Maybe @moidx is the best person to answer here though
Discussed with @moidx in the triage meeting and we've confirmed all relevant work is done here from the open source side, too. We can close this.
I will open a new issue to track the porting back of the timing constraints into the open source.
Evaluate what timing signoff is required for additional IO voltage corners.