Closed msfschaffner closed 7 months ago
@vogelpi / @h-filali - as an observer it looks like there have been quite a few changes so DV effort might be under-represented here now. Please update as appropriate.
git rev-parse --short HEAD
a47ab77591
git log Earlgrey-M2.5.2-RC0..HEAD --oneline hw/ip/entropy_src
54661e6ec7 [entropy_src] Reduce depth of Observe FIFO
2d82cc8e86 [entropy_src] Rework the swread packer FIFO to reduce area
fcd7af1c1a [entropy_src] Reduce depth of esfinal FIFO from 4 to 3 entries
-> changes to reduce area for M2
4e422bd8c8 [entropy_src/dv] Test whether noise source symbols are not dropped
2b8870ccd4 [entropy_src] Align enable delay module with fixed CS AES Halt interface 534a41e1df [entropy_src] Remove unneeded main SM state and input signals 0b88a66068 [entropy_src/dv] Reduce max delay for CS AES Halt IF in max rate test -> related to fixing the CS AES halt request interface
74a6e9b8b0 [entropy_src] Add FIFO to deal with backpressure from the conditioner -> required for FIPS compliance c2c27db812 [entropy_src] Align prim_fifo_sync instantiation parameters -> Improving security 7ebb11a7a7 [entropy_src] Fix FIFO controls, move drop point to before postht FIFO -> required for FIPS compliance f76a236c19 [entropy_src] Fix a Verilator lint warning
21adde16af [entropy_src] Fix CS AES Halt interface 15f75fa343 [kmac, sha3] Add REQ/ACK interface to delay Keccak operations 01b73a04ee [entropy_src/dv] Fix usage of rng_max_delay plusarg 2b9338d8f0 [entropy_src/dv] Fix CS AES Halt agent configuration -> helps saving power, required to properly assess conditioner back pressure, relevant for FIPS compliance
043b0e0783 [kmac] Simplify randomness update requests and PRNG control logic -> not related to ENTROPY_SRC e0a5f9db75 [entropy_src] Remove line diabling TRNG when esrng FIFO is full -> required for FIPS compliance 3eadcfde85 [entropy_src/rtl] Change the mubi4 true test to loose 03afa4c901 [entropy_src/rtl] Keep applying fw_ov_rd_fifo_overflow instead of pulsing -> bug fixs
381ccf9610 [entropy_src/rtl] Move the esbit FIFO down in sv file ea70f008a2 [entropy_src/doc] Move the esbit packer FIFO in the block diagram 0b2545191d [entropy_src/doc] Align the documentation with the moved esbit FIFO c35040febc [entropy_src/dv] Adapt the scoreboard to the repositioned esbit FIFO 46fe1942f8 [entropy_src/rtl] Move back 1-4 packer -> for de-risking FIPS certification
29866cc72d [entropy_src/doc] Adapt documentation to the new CONF register changes 03298b505a [entropy_src/dv] Add coverage for the new CONF changes b3b4207aa1 [entropy_src/dv] Align DV with new fips_flag changes 6b5f40ff29 [entropy_src/rtl] Use the new fips_flag registers 55763e1639 [entropy_src/rtl] Add new fips fields to CONF register -> for de-risking FIPS certification, enable OTBN operating in firmware override: extract and insert mode
0528bc24b6 [entropy_src/doc] Document how to use fw_ov mode with bypass 0604938ba1 [entropy_src/dv] Fix a failing rng_vseq test fae3235ce5 [dv/csr_utils] Change csr_peek to return the peeked value 79be09f3a4 [entropy_src/doc] Document operation upon health tests failures 809ba9c2b1 [entropy_src/doc] Document behavior of SHA3 conditioner engine
3f447cc12b [otp_ctrl] Remove entropy_src chicken switches -> these switches need to remain enabled in PROD to enable KAT of the conditioner and the firmware override modes
c721c51c13 [rtl, prim] Add 'commit' functionality to prim_count 61a237e197 [util/reggen] reverse order of substruct generation -> not specifically related to ENTROPY_SRC
e0a3193502 [doc] Clearly expand PTRNG acronym in entropy_src
de31bdf1c2 [reggen] Remove the devmode input 963a5006cc [doc] Minor tweak to md sanitisation code -> not specifically related to ENTROPY_SRC
b0fb96ac0b [es/dv] Add test_es_health_test_failed task to intr vseq 316431f907 [es/dv] Get intr vseq working again 50ecc0222f [es/dv] Add interrupt test f192e3e346 [es/dv] Add interrupt checks to the error vseq 975a6eb927 [adc_ctrl,dv] Tidy up access to intr_state in env_cfg files a5a80a6f85 [chip-test] List ENTROPY_SRC functional features d940eaab2b [doc] Add extra links to registers and fields for entropy_src d3326c1a16 [doc] Fix entropy_src links to renamed registers 1b16ca2122 [reggen] Add mubi support SWAccess that sets/clears a reg
59f8142826 [doc] Moved badges over to using hosted images -> not specifically related to ENTROPY_SRC
7688e714e8 [reggen] Add initial support for version and cip_id hjson fields fbd888eea8 Revert "[reggen] Add CIP_IDs and bump all major versions" 9b974b15ae [doc] entropy_src registers now using CMDGEN 0ba10b3cd3 [reggen] Add CIP_IDs and bump all major versions
Chip-level test / SiVal issue, it got decided that this better tested on the chip.
RTL change implemented and DV aligned with #21626
Chip-level test / SiVal issue, got removed with #21118.
Closed as not planned.
Closed as not planned.
Not specifically ENTROPY_SRC related.
RTL change implemented and DV aligned with #21787
DV
DV, fixed, it turned out the project was using a single deterministic seed for all simulations for some time.
RTL change implemented and DV aligned with #21685, a second PR #21799 was needed to fix the back pressure for good. Some DV / SW items remain. This is tracked as part of #21855.
RTL change implemented and DV aligned with #21369.
SiVal tests implemented with #21150 and #21562
DV task taken care of with #21821
Replacement issue for #11207, RTL change implemented and DV aligned with #21626
Bug fixed with #21640
SiVal
Sival
SiVal
SiVal
SiVal
Closed as not planned
Closed with #21799
ROM_EXT
Not specific to ENTROPY_SRC, recommendation is to formulate guidance for future designs, tracked in #20680
Entropy complex issue, future release
Cryptolib
Cryptolib
Options for power saving, related to #22293 and #22223.
DV, not relevant for Prod as Earlgrey doesn't implement external health tests
Not relevant for ENTROPY_SRC anymore. The corresponding test got removed with #21118.
Not relevant for Earlgrey, Darjeeling only.
Tracked as part of D3 / M4.
ROM_ext
Tracked as part of V3 / M5.
Tracked as part of V3 / M5.
Tracked as part of V3 / M5.
Tracked as part of V3 / M5, but can likely be closed now.
Cryptolib, duplicate of #2111
SiVal, Not specific to ENTROPY_SRC
Addressed by #22324
SiVal
Follow-up DV and software work, tracked as part of M4
Tracked as part of V2(S) / M4.
Not ENTROPY_SRC specific
Power saving discussions
RTL feature request
Integration question, mostly covered by currently available documentation.
Duplicate of #2111 and #19392.
RTL and chip-level test items covered, ROM_ext part open
Verification of hardened prim_fifo_sync
primitives as part of V2S / M4.
As part of M2, the following main RTL changes have been done. Unless stated below, DV and documentation have been updated inline with the RTL change:
Some of these changes break API compatibility , thus the version needs to be increased which is happening with this outstanding PR #22327
Despite pushing hard to keep the DV aligned with the RTL to not break things (and doing really a great job @h-filali ) we unfortunately don't meet the coverage metrics anymore to sign of at V2(S) again. Pass rates are still really good (all tests above 94%) but the coverage dropped. The reason for the coverage drop is twofold:
Both these things are tracked in https://github.com/lowRISC/opentitan/issues/21888.
My suggestion is to sign ENTROPY_SRC v.2.0.0 off at V1.
@andreaskurth , @h-filali , please let me know what you think.
Signing entropy_src off at V1 SGTM. Thx for the detailed signoff analysis, @vogelpi! :+1:
Description
Ensure V1 signoff criteria are fulfilled after focus area changes have landed.