[chip-test] chip_sw_adc_ctrl_sleep_debug_cable_wakeup

[johngt]

Test point name

chip_sw_adc_ctrl_sleep_debug_cable_wakeup

Host side component

Rust?

Opentitantool infrastructure implemented

Yes

Silicon Validation (SiVal)

Yes

Emulation targets

• [ ] None
• [ ] CW310
• [ ] Hyperdebug + CW310

Contact person

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

• [ ] Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
• [ ] Device-side (C) component developed
• [ ] Bazel build rules developed
• [ ] Host-side component developed
• [ ] Test added to dvsim nightly regression (and passing at time of checking)
• [ ] For SiVal test cases, test is running relevant FPGA or silicon regression

[matutem]

This test needs to inject specific activity in the adc_ctrl, which is only feasible in sim_dv. The test already works in sim_dv, so perhaps this needs to be closed.