[test-triage] i2c_csr_bit_bash test regression

nbdd0121 commented 1 month ago

Hierarchy of regression failure

Block level

Failure Description

DV report: https://reports.opentitan.org/hw/ip/i2c/dv/latest/report.html

1.i2c_csr_bit_bash.16988704953647101874499627179291902511050649595744511763604360769600393353891
Line 249, in log /container/opentitan-public/scratch/os_regression/i2c-sim-vcs/1.i2c_csr_bit_bash/latest/run.log

  UVM_ERROR @  16478540 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.acq_fifo_next_data reset value: 0x0 Wrote i2c_reg_block.acq_fifo_next_data[0]: 1
  UVM_INFO @  16478540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Steps to Reproduce

GitHub Revision: 4fd94db59a
dvsim random seed: --build-seed 89274329416853274976097168471417145417282051311181377329444669936981619711436

Tests with similar or related failures

[ ] i2c_csr_aliasing
[ ] i2c_csr_rw
[ ] i2c_tl_intg_err

This failure looks related:

[ ] i2c_same_csr_outstanding

a-will commented 1 month ago

Oops, probably I needed to exclude that CSR from some checks. I'm kind of surprised anything is run, since it's hwext and read-only for software.

a-will commented 1 month ago

Probably need to exclude the FIFO write CSRs from bit bash, too. It seems they get written enough times to fill up, then the test fails on the next write. It causes an assertion failure for wvalid remaining high until completion in i2c_fifos.

lowRISC / opentitan