Open AndySecqai opened 4 months ago
There's a step missing from the guide, sorry about that.
This _fpga_cw340_rom_with_fake_keys
suffix is actually expecting to find an STM32L552ZE Nucleo board plugged into the top of the CW340 running the HyperDebug firmware. It's set up that way since we're using that board configuration in our CI.
Would you mind trying with this patch? EDIT: updated.
diff --git a/hw/top_earlgrey/BUILD b/hw/top_earlgrey/BUILD
index c757417b7b..46fc3d88ac 100644
--- a/hw/top_earlgrey/BUILD
+++ b/hw/top_earlgrey/BUILD
@@ -271,7 +271,7 @@ fpga_cw340(
"--interface={interface}",
] + select({
"@//ci:lowrisc_fpga_cw340": ["--uarts=/dev/ttyACM_CW340_1,/dev/ttyACM_CW340_0"],
- "//conditions:default": [],
+ "//conditions:default": ["--uarts=/dev/ttyUSB2,/dev/ttyUSB3"],
}),
design = "earlgrey",
exec_env = "fpga_cw340",
@@ -281,7 +281,7 @@ fpga_cw340(
],
linker_script = "//sw/device/lib/testing/test_framework:ottf_ld_silicon_creator_slot_a",
param = {
- "interface": "hyper340",
+ "interface": "cw340",
"exit_success": DEFAULT_TEST_SUCCESS_MSG,
"exit_failure": DEFAULT_TEST_FAILURE_MSG,
},
@@ -343,7 +343,7 @@ fpga_cw340(
manifest = "//sw/device/silicon_owner:manifest_standard",
otp = "//sw/device/silicon_creator/rom_ext/e2e:otp_img_secret2_locked_rma",
param = {
- "interface": "hyper340",
+ "interface": "cw340",
"exit_success": DEFAULT_TEST_SUCCESS_MSG,
"exit_failure": DEFAULT_TEST_FAILURE_MSG,
"assemble": "{rom_ext}@0 {firmware}@0x10000",
Sorry, I haven't checked it myself, but this tells OpenTitanTool to look for the CW340's SAM3X chip as the interface instead of the HyperDebug board.
Also, make sure the big ribbon jumper cables on your board are configured for the SAM3X (and not HD of FTDI).
Applied that change:
git diff hw/top_earlgrey/BUILD
diff --git a/hw/top_earlgrey/BUILD b/hw/top_earlgrey/BUILD
index 9a26a4fe4d..fdb345e5a2 100644
--- a/hw/top_earlgrey/BUILD
+++ b/hw/top_earlgrey/BUILD
@@ -283,7 +283,7 @@ fpga_cw340(
],
linker_script = "//sw/device/lib/testing/test_framework:ottf_ld_silicon_creator_slot_a",
param = {
- "interface": "hyper340",
+ "interface": "cw340",
"exit_success": DEFAULT_TEST_SUCCESS_MSG,
"exit_failure": DEFAULT_TEST_FAILURE_MSG,
},
which appears to have changed (improved?) things:
./bazelisk.sh test --test_output=streamed //sw/device/tests:uart_smoketest_fpga_${BOARD}_rom_with_fake_keys
WARNING: Streamed test output requested. All tests will be run locally, without sharding, one at a time
INFO: Analyzed target //sw/device/tests:uart_smoketest_fpga_cw340_rom_with_fake_keys (0 packages loaded, 0 targets configured).
INFO: Found 1 test target...
Invoking test: sw/host/opentitantool/opentitantool --rcfile= --logging=info --interface=cw340 --exec=transport init --exec=fpga load-bitstream hw/bitstream/universal/splice.bit --exec=bootstrap --clear-uart=true sw/device/tests/uart_smoketest_fpga_cw340_rom_with_fake_keys.test_key_0.signed.bin --exec=console --non-interactive --exit-success='PASS.*\n' --exit-failure='((FAIL|FAULT).*\n)|(BFV:[0-9a-f]{8})' no-op
[2024-05-01T10:46:35Z INFO opentitantool] Command result: success.
[2024-05-01T10:46:35Z INFO opentitantool::command::load_bitstream] Loading bitstream: "hw/bitstream/universal/splice.bit"
[2024-05-01T10:46:35Z INFO opentitanlib::util::usr_access] Bitstream file USR_ACCESS value: 0xde9096dd
[2024-05-01T10:46:37Z INFO opentitanlib::util::rom_detect] Did not detect the ROM identification message.
[2024-05-01T10:46:37Z INFO opentitanlib::transport::chip_whisperer] Programming the FPGA bitstream.
[2024-05-01T10:46:58Z INFO opentitantool] Command result: success.
[2024-05-01T10:46:58Z INFO opentitanlib::bootstrap] Asserting bootstrap pins...
[2024-05-01T10:46:58Z INFO opentitanlib::app] Asserting the reset signal
[2024-05-01T10:46:58Z INFO opentitanlib::app] Clearing the UART RX buffer
[2024-05-01T10:46:58Z INFO opentitanlib::app] Deasserting the reset signal
[2024-05-01T10:46:58Z INFO opentitanlib::bootstrap] Performing bootstrap...
[2024-05-01T10:46:58Z INFO opentitanlib::bootstrap] Releasing bootstrap pins, resetting device...
[2024-05-01T10:46:58Z INFO opentitanlib::app] Asserting the reset signal
[2024-05-01T10:46:58Z INFO opentitanlib::app] Deasserting the reset signal
[2024-05-01T10:46:58Z INFO opentitantool] Command result: SFDP header contains incorrect signature: 0xffffffff
Stack backtrace:
0: <core::result::Result<T,F> as core::ops::try_trait::FromResidual<core::result::Result<core::convert::Infallible,E>>>::from_residual
1: opentitanlib::spiflash::flash::SpiFlash::read_sfdp
2: opentitanlib::spiflash::flash::SpiFlash::from_spi
3: <opentitanlib::bootstrap::eeprom::Eeprom as opentitanlib::bootstrap::UpdateProtocol>::update
4: opentitanlib::bootstrap::Bootstrap::do_update
5: opentitanlib::bootstrap::Bootstrap::update_with_progress
6: <opentitantool::command::bootstrap::BootstrapCommand as opentitanlib::app::command::CommandDispatch>::run
7: opentitantool::_::<impl opentitanlib::app::command::CommandDispatch for opentitantool::RootCommandHierarchy>::run
8: opentitantool::execute
9: opentitantool::main
10: core::ops::function::FnOnce::call_once
11: std::sys_common::backtrace::__rust_begin_short_backtrace
12: std::rt::lang_start::{{closure}}
13: core::ops::function::impls::<impl core::ops::function::FnOnce<A> for &F>::call_once
at /rustc/32303b219d4dffa447aa606bc11c7a648f44a862/library/core/src/ops/function.rs:284:13
std::panicking::try::do_call
at /rustc/32303b219d4dffa447aa606bc11c7a648f44a862/library/std/src/panicking.rs:524:40
std::panicking::try
at /rustc/32303b219d4dffa447aa606bc11c7a648f44a862/library/std/src/panicking.rs:488:19
std::panic::catch_unwind
at /rustc/32303b219d4dffa447aa606bc11c7a648f44a862/library/std/src/panic.rs:142:14
std::rt::lang_start_internal::{{closure}}
at /rustc/32303b219d4dffa447aa606bc11c7a648f44a862/library/std/src/rt.rs:148:48
std::panicking::try::do_call
at /rustc/32303b219d4dffa447aa606bc11c7a648f44a862/library/std/src/panicking.rs:524:40
std::panicking::try
at /rustc/32303b219d4dffa447aa606bc11c7a648f44a862/library/std/src/panicking.rs:488:19
std::panic::catch_unwind
at /rustc/32303b219d4dffa447aa606bc11c7a648f44a862/library/std/src/panic.rs:142:14
std::rt::lang_start_internal
at /rustc/32303b219d4dffa447aa606bc11c7a648f44a862/library/std/src/rt.rs:148:20
14: std::rt::lang_start
15: main
16: __libc_start_call_main
at ./csu/../sysdeps/nptl/libc_start_call_main.h:58:16
17: __libc_start_main_impl
at ./csu/../csu/libc-start.c:392:3
18: _start
Error: SFDP header contains incorrect signature: 0xffffffff
Stack backtrace:
0: <core::result::Result<T,F> as core::ops::try_trait::FromResidual<core::result::Result<core::convert::Infallible,E>>>::from_residual
1: opentitanlib::spiflash::flash::SpiFlash::read_sfdp
2: opentitanlib::spiflash::flash::SpiFlash::from_spi
3: <opentitanlib::bootstrap::eeprom::Eeprom as opentitanlib::bootstrap::UpdateProtocol>::update
4: opentitanlib::bootstrap::Bootstrap::do_update
5: opentitanlib::bootstrap::Bootstrap::update_with_progress
6: <opentitantool::command::bootstrap::BootstrapCommand as opentitanlib::app::command::CommandDispatch>::run
7: opentitantool::_::<impl opentitanlib::app::command::CommandDispatch for opentitantool::RootCommandHierarchy>::run
8: opentitantool::execute
9: opentitantool::main
10: core::ops::function::FnOnce::call_once
11: std::sys_common::backtrace::__rust_begin_short_backtrace
12: std::rt::lang_start::{{closure}}
13: core::ops::function::impls::<impl core::ops::function::FnOnce<A> for &F>::call_once
at /rustc/32303b219d4dffa447aa606bc11c7a648f44a862/library/core/src/ops/function.rs:284:13
std::panicking::try::do_call
at /rustc/32303b219d4dffa447aa606bc11c7a648f44a862/library/std/src/panicking.rs:524:40
std::panicking::try
at /rustc/32303b219d4dffa447aa606bc11c7a648f44a862/library/std/src/panicking.rs:488:19
std::panic::catch_unwind
at /rustc/32303b219d4dffa447aa606bc11c7a648f44a862/library/std/src/panic.rs:142:14
std::rt::lang_start_internal::{{closure}}
at /rustc/32303b219d4dffa447aa606bc11c7a648f44a862/library/std/src/rt.rs:148:48
std::panicking::try::do_call
at /rustc/32303b219d4dffa447aa606bc11c7a648f44a862/library/std/src/panicking.rs:524:40
std::panicking::try
at /rustc/32303b219d4dffa447aa606bc11c7a648f44a862/library/std/src/panicking.rs:488:19
std::panic::catch_unwind
at /rustc/32303b219d4dffa447aa606bc11c7a648f44a862/library/std/src/panic.rs:142:14
std::rt::lang_start_internal
at /rustc/32303b219d4dffa447aa606bc11c7a648f44a862/library/std/src/rt.rs:148:20
14: std::rt::lang_start
15: main
16: __libc_start_call_main
at ./csu/../sysdeps/nptl/libc_start_call_main.h:58:16
17: __libc_start_main_impl
at ./csu/../csu/libc-start.c:392:3
18: _start
cleanup:
FAIL: //sw/device/tests:uart_smoketest_fpga_cw340_rom_with_fake_keys (see /home/admin-sqai/.cache/bazel/_bazel_admin-sqai/a9589ee45fb4114764ac879aea12063a/execroot/lowrisc_opentitan/bazel-out/k8-fastbuild-ST-2cc462681f62/testlogs/sw/device/tests/uart_smoketest_fpga_cw340_rom_with_fake_keys/test.log)
INFO: Elapsed time: 24.422s, Critical Path: 24.18s
INFO: 2 processes: 2 local.
INFO: Build completed, 1 test FAILED, 2 total actions
//sw/device/tests:uart_smoketest_fpga_cw340_rom_with_fake_keys FAILED in 24.1s
/home/admin-sqai/.cache/bazel/_bazel_admin-sqai/a9589ee45fb4114764ac879aea12063a/execroot/lowrisc_opentitan/bazel-out/k8-fastbuild-ST-2cc462681f62/testlogs/sw/device/tests/uart_smoketest_fpga_cw340_rom_with_fake_keys/test.log
Executed 1 out of 1 test: 1 fails locally.
This appears to have done something to the FPGA, but I'm just getting the following printing continuously:
VER:4ROM:de9096dd
BFV:0142500d
LCV:2739ce73
VER:4ROM:de9096dd
BFV:0142500d
LCV:2739ce73
VER:4ROM:de9096dd
BFV:0142500d
LCV:2739ce73
VER:4ROM:de9096dd
BFV:0142500d
LCV:2739ce73
VER:4ROM:de9096dd
BFV:0142500d
LCV:2739ce73
VER:4ROM:de9096dd
BFV:0142500d
LCV:2739ce73
VER:4ROM:de9096dd
BFV:0142500d
LCV:2739ce73
VER:4ROM:de9096dd
In terms of jumper cables - I'm not sure what you mean by "the big one" and this doesn't appear to be documented anywhere? Please see attached our current configuration which is basically as it was out of the box:
Ah, I'm talking about the white ribbon cables as configured here:
That one on the right connects all the SPI pins which is what flash programming goes over (the SFDP error means the flash isn't programmed right). It looks like you're jumping just one cable there.
I couldn't get bazel test
to see the UART output but I could see it directly from the tty
s, so there's probably a bug in the opentitantool console.
I've updated the patch in https://github.com/lowRISC/opentitan/issues/22913#issuecomment-2088268508 to something which fixes the UARTs for bazel test
.
Description
I have followed the setup process for a new CW340 card, however am unable to get any of the bazel tests to dispatch to the board.
Communication to the board appears to be working correctly:
and I can program the FPGA:
which gives the expected boot-time console printing with
screen /dev/ttyUSB2 115200,cs8,-ixon,-ixoff
:However, trying to dispatch a test gives an
Error: Found no USB device
:Is there a step missing in the setup guide? Is there supposed to be more than the one USB connection to J28?
Thanks, Andy