[test-triage] Chip_sw_uart_tx_rx_bootstrap timeout

[pamaury]

Hierarchy of regression failure

Chip Level

Failure Description

Timeout

Steps to Reproduce

• GitHub Revision: 9656691e03
• dvsim invocation command to reproduce the failure, inclusive of build and run seeds: ./util/dvsim/dvsim.py hw/top_earlgrey/dv/chip_sim_cfg.hjson -i chip_sw_uart_tx_rx_bootstrap --build-seed 30170103562476460183108208532025718695603957360441815475011549460912256789439 --fixed-seed 38902495902850271867553058495145156207109662916179471927802333451347076119242 --waves fsdb
• Kokoro build number if applicable

Tests with similar or related failures

• [ ] Test_name_1
• [ ] Test_name_2

[pamaury]

Ping @a-will

[a-will]

It's just a very long-running test that is sensitive to the performance and load of the machine that is running it. This particular failure instance passes locally. The timeout likely needs to be increased to pass more reliably on the infrastructure.

We spend something like 75 us of simulation time merely performing bootstrap, here...