Open ballifatih opened 5 months ago
The following is addressed by both of these PRs (once merged): https://github.com/lowRISC/opentitan/pull/24839 and https://github.com/lowRISC/opentitan/pull/24944
"Consider whether we want to have a timeout value for polling for interrupt signal. HMAC does not use EDN, so we should be able to determine a reasonable timeout value."
Description
(this issue is WIP)
RV_CORE_IBEX_RND_STATUS_REG_OFFSET
.sha256/sha512
files related to OTBN.And potential improvement suggestions for SCA/FI hardening:
hardened_memcpy
) for KEY and DIGEST registers. This can also be extended to message inputs if message bits are also sensitive, depending on the use case (e.g. HMAC-DRBG).hw_started
flag.ctx
after the final call makes sense. If so, the values could be populated with random values. The suggestion is to zeroise or randomly populatectx
struct during init.hmac_en
and use it to skip key writing etc. https://github.com/lowRISC/opentitan/pull/23196#discussion_r1609013103