[pattgen,doc] Documentation might not be up to date

[pamaury]

Description

The following issues were found when when porting the pattgen_ios_test to master.

• When the inactive level feature was added in #23198, the Theory of operation section was not update and only the programmers' guide explains the inactive feature. This can be misleading this the theory of operations says that: When this overflow occurs, the FSM transitions to the END state. All counters halt, the pda data lines reset to zero, and an interrupt event is sent out to signal completion. Maybe the theory of operation should be updated as well to mention to the inactive levels instead of zero.

• Another issue is that based on the RTL, the inactive level bits can only be changed when the channel is not enabled but this is not specified in the register documentation. This is in constrast to the other fields that have a comment saying Note that writes to a channel’s configuration registers have no effect while

• The interaction between the inactive level and polarity features does not seem clear to me (see below).

Inactive level and polarity feature

The documentation says For either channel, a zero in the polarity bit indicates that the channel clock line (pcl) should start low, and the channel data line pda transitions on every falling edge of pcl. A one in the polarity bit inverts the pcl clock so that it starts high and pda transitions on the rising edge.. However it can lead to unclear situations (which to be fair already existed somewhat before this feature). For example if the polarity is set to rising edge and the inactive level pcl is set to high then on the first "clock tick", PCL is already high so it does not technically have a rising edge. Will the data change on that non-existent rising edge or will it wait until the lock actually falls low and rises again?

[pamaury]

@andreaskurth might be relevant for M4?