[test-triage] `sram_ctrl/{main,ret}:sram_ctrl_stress_all{,_with_rand_reset}`

HU90m commented 4 months ago

Hierarchy of regression failure

Block level

Failure Description

UVM_WARNING @ 35309663403 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "en" while containing register "sram_ctrl_regs_reg_block.readback" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.

Steps to Reproduce

GitHub Revision: 8cb25a6867

./util/dvsim/dvsim.py hw/ip/sram_ctrl/dv/sram_ctrl_main_sim_cfg.hjson -i sram_ctrl_stress_all \
    --build-seed 26638040090898561482658723926798947801831709189350919955228328310045202344042 \
    --fixed-seed 95406650109520020538065943561764986450042451907920781657771145504888113370195

The two changes made to this block between it passing and failing are https://github.com/lowRISC/opentitan/pull/23212 and https://github.com/lowRISC/opentitan/pull/23292 .

Tests with similar or related failures

The following also broke at the same time.

nasahlpa commented 4 months ago

This will be fixed once #23360 has been merged.

vogelpi commented 4 months ago

Closing as #22360 has been merged now.

lowRISC / opentitan