antmarzam
commented
4 weeks ago DESIGN_DELTAS_CAPTURED_V2
List of commits since ES. The list has been compiled via:
git log Earlgrey-M2.5.2-RC0..HEAD hw/ip/spi_device/ hw/dv/sv/spi_agent/All the commits covered in V1 sign-off have been taken out of the list.
Newer commits at the top:
- ee5f4a1abf [sram_ctrl] Add readback feature
- RTL change to SRAM
- 1f05782f8d [spi_device] Add CSB reset sync for outclk domain
- RTL fix for unsafe reset timing
- 1fafdaf22e [dv] Spi_device CFG register Covergroup fix.
- spi_device CFG register FCOV update according to RTL changes
- 07352ce012 [dv] TB fixes for timeouts
- TB changes to reduce chances of timeouts
- 12f60880bd [dv] spi_device_scoreboard flash_status fix
- TB flash status fix to allow RTL changes to be tested
- 8ebf451ed7 [dv] spi_device_pass_base_vseq backpressure fix
- TB fix when there's backpressure and a TLUL read/write takes time until the response is accepted
- a7dafe6ef6 [dv] Disable spi_device_intercept_vseq 'two_writes' option
- Disable TB flash_status write combination which won't happen in SW
- 432200b06e [dv] spi_monitor fix:
- spi byte and termination events won't fire for TPM since these are only used in flash_mode and flash side of RTL won't update on TPM being active.
- 84372e3bb6 [dv] spi_device_env_cfg: new Flag set by SCB on flash command
- TB flag for VSEQs syncing
- 854377469f [spi_device] Track intercept_en along the read pipeline
- RTL change which fixes the RTL not dropping the last 2-bit/4-bit/8-bit in a SPI command
- dc848b3e2a [sram_ctrl,prim,rtl] Fix tlul_we -> ready timing path.
- e5743c1e1d [spi_device,dv] Lower the reseed count for spi_device_ram_cfg
- a937d7678a [spi_device] Replace prim_ram_2p_adv by prim_ram_2p_async_adv dependency
- Prim replacement
- df40ae5d62 [spi_device] Fix lint error
- Lint error fix reported by Nuvoton
- 8295903d7e [bazel,autogen_hjson] Split C and rust header generation
- Bazel change
- 30d7e787c7 Add the project name to the copyright header
- header change across project
- ec43583573 [dv] intercept sequence && intr_status stimulus update
- TB changes to intercept sequence so reads/writes to flash_status won't only occur while the SPI interface is idle
- 42dfffeb8c [dv] flash_status dynamically updated TB update
- TB changes to model, exercise and test flash_status RTL changes
- 18b0cedda1 [dv] Remove phase argument from monitor's collect_trans
- cleanup UVM monitors across project
- 5fe7bfed1a [spi_device] Match OE with the passthrough read pipeline data
- RTL fix to sync
sd_en_owith read_pipeline signals in passthrough mode
- RTL fix to sync
- 75cb3b901e [spi_device,dv] Generalise description of mem_cfg testpoint
- testplan mem configuration amendment
- 67ffe9a61c [dv] fix spi_device dvsim output path
- Double-variant module IT fix
- 13783951da [dv_doc] spi_device dv doc generic mod and 2P SRAM mentions removal
- Doc cleanup
- dd3395ee60 [dv] intr_state variable for predicted value
- TB fix
- cb1e8e8948 [dv] Read buffer watermark interrupt fix
- TB fix
- 4f88e076ec [spi_device,dv] Split sim config into separate 1r1w and 2p versions
- cf1d83ff97 [spi_device] Sign off for D2 and D2S
- 73b61d0b53 [dv] Update spi-device testplan for V1 sign-off.
- aa8d343148 [dv] SPI Device testplan generic mode removal
- fb0fae4971 [spi_device] Update the checklist for current state
- f0490a55bb [spi_device] Remove abandoned TODOs
- more RTL file cleanup
- 11f93a0879 [spi_device] Add missing not-X assertions for output ports
- c0132295cf [spi_device] Explain the SRAM split and access
- Doc change
- 3f6f08aa8b [spi_device] Add issue number for ignoring commands while busy
- d1f4251212 [spi_device] Remove outdated TODOs
- doc + RTL cleanup
- ea60d5fd55 [spi_device] Add mechanism to reset the flash read buffer
- RTL change to allow SW to flush read buffer
Apart from the issues above, there are a couple of TB related Spi_device PRs open:
DV_DOC_COMPLETED
All RTL changes have been reflected in the spec
FUNCTIONAL_COVERAGE_IMPLEMENTED
Functional coverage for new features has been implemented
ALL_INTERFACES_EXERCISED
Yes
ALL_ASSERTION_CHECKS_ADDED
Yes - except for the open ticket
SIM_TB_ENV_COMPLETED
Yes
SIM_ALL_TESTS_PASSING
Not true in an absolute manner but true for our metrics. Currently there are between 0/1 failures per overnight regression run which runs 1101 tests
SIM_NIGHTLY_REGRESSION_V2
Yes, current passing rate is very high as there's 0/1 failure per run
SIM_CODE_COVERAGE_V2
Yes, although there is an issue with the path in an RTL waiver file and the FSM numbers for passtrough are low, but that feature is unsupported and hence waivable.
SIM_FUNCTIONAL_COVERAGE_V2
Yes, current metric is 99.25% for FCOV
SEC_CM_PLANNED
Yes, and already implemented
NO_HIGH_PRIORITY_ISSUES_PENDING, ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED
No P0/1 issues Low priority only issue
DV_DOC_TESTPLAN_REVIEWED
No change here
V3_CHECKLIST_SCOPED
The checklist hasn't been scoped, but given the coverage numbers (shown below). I anticipate an effort of up to 2 weeks to close coverage and do the necessary cleanup
COVERAGE NUMBERS as of 2/6/24
Note: FPV and SIM_FW_SIMULATED have been removed from above list since they don't apply to spi device.
a-will
rswarbrick
Description
Get spi_device ready for V2S signoff and sign it off