[hmac,dv] Various assertions

[martin-velay]

Description

Here below is the list of potential assertions to be added to the DV

Note: is to be discussed

STATUS	NAME	DESCRIPTION (extracted from the spec)
TODO?	Wipe secret key	The secret key could be wipped from several internal RTL registers such as secret key, internal state machine, or hash value. Internal values are replaced or XORed with the written value in WIPE_SECRET register.
TODO?	HMAC core block FIFO size	HMAC core contains a 32x32-bit size FIFO
TODO?	SHA-2 block FIFOs sizes	SHA-2 block contains two time a 8x64-bit size FIFOs (one for the hash and one for the digest)
TODO?	Writes while FIFO is full	If the FIFO is full, the HMAC block will block any writes leading to back-pressure on the interconnect.
TODO?	Message endianness swap	When CFG.endian_swap=1, input message is converted from little-endian to big-endian before feeding it to the SHA-2
TODO?	Digest endianness swap	When CFG.digest_swap=1, each digest output register is converted to big-endian byte order
TODO?	HMAC extra latency	HMAC should introduce a latency equals to 240 extra cycles
TODO?	Digest clear	DIGEST registers should be cleared when transition 1->0 on CFG.sha_en
TODO?	DIGEST registers write	DIGEST registers should be writtable when CFG.sha_en=0, check also that they cannot be written when CFG.sha_en=1
TODO?	Message length	The received Message Length calculated by the HMAC should match with these registers value such as: message_length[63:0]={MSG_LENGTH_UPPER, MSG_LENGTH_LOWER}. In SHA-256 mode all 64 bits are used, but in SHA-384/512, upper 64 bits are zero padded and only {MSG_LENGTH_UPPER, MSG_LENGTH_LOWER} are actually checked.
TODO?	MSG_LENGTH registers write	MSG_LENGTH registers should be writtable only when CFG.sha_en=0, check also that they cannot be written when CFG.sha_en=1
TODO?	MSG_LENGTH_LOWER register LSBs	Message length granularity should be in bytes, and these registers express it in bits, so the 3 LSBs from MSG_LENGTH_LOWER should be always zeros
TODO?	INTR_STATE.fifo_empty register field	FIFO empty status interrupt

[andreaskurth]

@martin-velay: Also for this issue: V3 and M7?

[martin-velay]

@andreaskurth: yes we can move it